公开(公告)号：US20170194245A1

公开(公告)日：2017-07-06

申请号：US14987211

申请日：2016-01-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj PATIL ,  Ajey Poovannummoottil JACOB ,  Shesh Mani PANDEY

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/76804 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/5283 ,  H01L28/40

Abstract: A method of providing on-chip capacitance includes providing a starting interconnect structure for semiconductor device(s), the starting interconnect structure including a layer of dielectric material. Vias of a same cross-sectional shape are formed in the layer of dielectric material having different and successive geometric cross-sectional size, and capacitors matching the via shape are formed in the vias. The geometric cross-sectional shapes include circles, squares, hexagons and octagons. For the non-circle shapes, a capacitance thereof is approximated by the capacitance of a coaxial capacitor fitting within and touching all sides of the non-circle shape multiplied by a correction factor of about 0.01 to about 2.