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公开(公告)号:US11664432B2
公开(公告)日:2023-05-30
申请号:US16556796
申请日:2019-08-30
Applicant: GLOBALFOUNDRIES U.S. INC.
Inventor: Dirk Utess , Zhixing Zhao , Dominik M. Kleimaier , Irfan A. Saadat , Florent Ravaux
IPC: H01L27/092 , H01L29/417 , H01L29/40 , H01L29/78
CPC classification number: H01L29/41775 , H01L27/092 , H01L29/401 , H01L29/7845
Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.
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2.
公开(公告)号:US10923594B2
公开(公告)日:2021-02-16
申请号:US16227059
申请日:2018-12-20
Applicant: GLOBALFOUNDRIES U.S. INC.
Inventor: Dirk Utess , Peter Philipp Steinmann , Stephanie Wilhelm
IPC: H01L29/78 , H01L21/8234 , H01L27/088
Abstract: One illustrative integrated circuit product disclosed herein comprises first and second spaced-apart P-active regions positioned on a buried insulation layer positioned on a base substrate, at least one first PFET transistor in the first P-active region, and a plurality of second PFET transistors in the second P-active region, wherein the first P-active region has a first length (in the gate length direction of the device) and the second P-active region has a second length that is greater than the first length and wherein the number of second PFET transistors is greater than the number of first PFET transistors. In this example, the product also includes a tensile-stressed layer of material positioned on the at least one first PFET transistor and above the first P-active region and a compressive-stressed layer of material positioned on the plurality of second PFET transistors and above the second P-active region.
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