公开(公告)号：US10991796B2

公开(公告)日：2021-04-27

申请号：US16231671

申请日：2018-12-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Lin Hu ,  Veeraraghavan S. Basker ,  Brian J. Greene ,  Kai Zhao ,  Daniel Jaeger ,  Keith Tabakman ,  Christopher Nassar

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: A dielectric fill layer within source/drain metallization trenches limits the depth of an inlaid metallization layer over isolation regions of a semiconductor device. The modified geometry decreases parasitic capacitance as well as the propensity for electrical short circuits between the source/drain metallization and adjacent conductive structures, which improves device reliability and performance.