公开(公告)号：US10991796B2

公开(公告)日：2021-04-27

申请号：US16231671

申请日：2018-12-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Lin Hu ,  Veeraraghavan S. Basker ,  Brian J. Greene ,  Kai Zhao ,  Daniel Jaeger ,  Keith Tabakman ,  Christopher Nassar

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: A dielectric fill layer within source/drain metallization trenches limits the depth of an inlaid metallization layer over isolation regions of a semiconductor device. The modified geometry decreases parasitic capacitance as well as the propensity for electrical short circuits between the source/drain metallization and adjacent conductive structures, which improves device reliability and performance.

公开(公告)号：US11069809B2

公开(公告)日：2021-07-20

申请号：US15884045

申请日：2018-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander Reznicek ,  Shogo Mochizuki ,  Veeraraghavan S. Basker ,  Nicolas L. Breil ,  Oleg Gluschenkov

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66

Abstract: Fabrication method for a semiconductor device and structure are provided, which includes: providing an isolation layer at least partially disposed adjacent to at least one sidewall of a fin structure extended above a substrate structure, the fin structure including a channel region; recessing an exposed portion of the fin structure to define a residual stress to be induced into the channel region of the fin structure, wherein upper surfaces of a recessed fin portion and the isolation layer are coplanar with each other; and epitaxially growing a semiconductor material from the recessed exposed portion of the fin structure to form at least one of a source region and a drain region of the semiconductor device.