公开(公告)号：US12087384B2

公开(公告)日：2024-09-10

申请号：US17668962

申请日：2022-02-10

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ming Yin ,  Bipul C. Paul ,  Nishtha Gaul ,  Shashank Nemawarkar

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C5/148

Abstract: The present disclosure relates to memory devices and, more particularly, to bias voltage generation circuit for memory devices and methods of operation. The voltage generation circuit includes: an internal voltage generator which providing a bias voltage to at least one internal node of a bias voltage generation circuitry; and at least one pre-charging circuitry providing a predefined bias voltage to at least one internal node including a distributed network of local drivers.

公开(公告)号：US12176053B2

公开(公告)日：2024-12-24

申请号：US17380688

申请日：2021-07-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ramesh Raghavan ,  Balaji Jayaraman ,  Ming Yin

IPC: G11C29/00 ,  G11C7/12 ,  G11C8/08 ,  G11C29/50

Abstract: The present disclosure relates to integrated circuits, and more particularly, to a wordline system architecture supporting an erase operation and current-voltage (I-V) characterization and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: a twin cell circuit which is connected to a wordline of a memory array; a sourceline driver which is connected to a sourceline of the memory array for providing a cell level current-voltage (I-V) access of the twin cell circuit; and an integrated analog multiplexor which is connected to the twin cell circuit.