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    Sense circuit and high-speed memory structure incorporating the sense circuit
    1.
    发明授权
    Sense circuit and high-speed memory structure incorporating the sense circuit 有权

    公开(公告)号：US12051465B2

    公开(公告)日：2024-07-30

    申请号：US17812485

    申请日：2022-07-14

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Chandrahasa Reddy Dinnipati ,  Bipul C. Paul ,  Ramesh Raghavan

    IPC: G11C13/00 ,  G11C11/16

    CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C2013/0054 ,  G11C2213/79

    Abstract: Disclosed is a sense circuit with first and second branches connected to first and second inputs of an amplifier. The first branch includes series-connected first transistors between a voltage rail and a data line and a first node between two first transistors and connected to the first input. First transistors on either side of the first node receive corresponding gate bias voltages. The second branch includes series-connected second transistors between the voltage rail and a reference device and a second node between two second transistors and connected to the second input. One first transistor and one second transistor share a common control signal. The first and second branches independently and concurrently generate data and reference voltages on the first and second nodes and the difference between them is sensed by the amplifier. Also disclosed are a non-volatile memory structure incorporating the sense circuit and a method.

    SENSE CIRCUIT AND HIGH-SPEED MEMORY STRUCTURE INCORPORATING THE SENSE CIRCIUT
    3.
    发明公开
    SENSE CIRCUIT AND HIGH-SPEED MEMORY STRUCTURE INCORPORATING THE SENSE CIRCIUT 审中-公开

    公开(公告)号：US20240021243A1

    公开(公告)日：2024-01-18

    申请号：US17812485

    申请日：2022-07-14

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Chandrahasa Reddy Dinnipati ,  Bipul C. Paul ,  Ramesh Raghavan

    IPC: G11C13/00 ,  G11C11/16

    CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C2213/79 ,  G11C2013/0054

    Abstract: Disclosed is a sense circuit with first and second branches connected to first and second inputs of an amplifier. The first branch includes series-connected first transistors between a voltage rail and a data line and a first node between two first transistors and connected to the first input. First transistors on either side of the first node receive corresponding gate bias voltages. The second branch includes series-connected second transistors between the voltage rail and a reference device and a second node between two second transistors and connected to the second input. One first transistor and one second transistor share a common control signal. The first and second branches independently and concurrently generate data and reference voltages on the first and second nodes and the difference between them is sensed by the amplifier. Also disclosed are a non-volatile memory structure incorporating the sense circuit and a method.

    Wordline system architecture supporting erase operation and I-V characterization
    5.
    发明授权
    Wordline system architecture supporting erase operation and I-V characterization 有权

    公开(公告)号：US12176053B2

    公开(公告)日：2024-12-24

    申请号：US17380688

    申请日：2021-07-20

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Ramesh Raghavan ,  Balaji Jayaraman ,  Ming Yin

    IPC: G11C29/00 ,  G11C7/12 ,  G11C8/08 ,  G11C29/50

    Abstract: The present disclosure relates to integrated circuits, and more particularly, to a wordline system architecture supporting an erase operation and current-voltage (I-V) characterization and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: a twin cell circuit which is connected to a wordline of a memory array; a sourceline driver which is connected to a sourceline of the memory array for providing a cell level current-voltage (I-V) access of the twin cell circuit; and an integrated analog multiplexor which is connected to the twin cell circuit.

    MEMORY ASSEMBLY WITH BODY BIASING AND RELATED METHODS
    6.
    发明公开
    MEMORY ASSEMBLY WITH BODY BIASING AND RELATED METHODS 审中-公开

    公开(公告)号：US20240304258A1

    公开(公告)日：2024-09-12

    申请号：US18178926

    申请日：2023-03-06

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Ramesh Raghavan ,  Chandrahasa Reddy Dinnipati ,  Philipp Bernhard Mosch

    IPC: G11C16/26 ,  G11C16/34

    CPC classification number: G11C16/26 ,  G11C16/34

    Abstract: Embodiments of the disclosure provide a memory assembly with body biasing and related methods to operate such a structure. A structure according to the disclosure includes a memory cell having a pair of memory transistors each having a gate coupled to a word line. A pair of diode-connected transistors each have a source/drain (S/D) terminal coupled to a respective S/D terminal of one of the pair of memory transistors through a multiplexer. A bias voltage source is coupled to each body of the pair of diode-connected transistors or each body of the pair of memory transistors. The bias voltage source applies a different bias voltage to each body of the pair of diode-connected transistors or each body of the pair of memory transistors.

    Twin cell memory-based physically unclonable function
    8.
    发明授权
    Twin cell memory-based physically unclonable function 有权

    公开(公告)号：US11329836B1

    公开(公告)日：2022-05-10

    申请号：US17199515

    申请日：2021-03-12

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Toshiaki Kirihata ,  Balaji Jayaraman ,  Chandrahasa Reddy Dinnipati ,  Ramesh Raghavan

    IPC: H04L9/32 ,  G11C7/06 ,  G11C8/10

    Abstract: A Physically Unclonable Function (PUF) structure includes an array of twin cells divided into two portions: one with first columns and one with second columns. Cells in each first column are connected to a corresponding pair of first bitlines. Cells in each second column are connected to a corresponding pair of second bitlines. A first column decoder is connected to the first bitlines and to a first input of sense amplifier (SA) and a second column decoder is connected to the second bitlines and to a second input of SA. Each read operation to generate a bit is directed to a first cell in a first column and a second cell in a second column and, during the read operation, signals on only one first bitline of the first column containing the first cell and only one second bitline of the second column containing the second cell are compared.

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