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公开(公告)号:US20220190108A1
公开(公告)日:2022-06-16
申请号:US17155469
申请日:2021-01-22
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Uzma B. Rana , Anthony K. Stamper , Steven M. Shank , Srikanth Srihari
Abstract: A transistor includes a bulk semiconductor substrate, and a first source/drain region in the bulk semiconductor substrate separated from a second source/drain region in the bulk semiconductor substrate by a channel region. A first air gap is defined in the bulk semiconductor substrate under the first source/drain region, and a second air gap is defined in the bulk semiconductor substrate under the second source/drain region. A gate is over the channel region. A spacing between the first air gap and the second air gap is greater than or equal to a length of the channel region such that the first and second air gaps are not under the channel region. The air gaps may have a rectangular cross-sectional shape. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.
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公开(公告)号:US11605710B2
公开(公告)日:2023-03-14
申请号:US17155469
申请日:2021-01-22
Applicant: GLOBALFOUNDRIES U.S. Inc.
Inventor: Uzma B. Rana , Anthony K. Stamper , Steven M. Shank , Srikanth Srihari
Abstract: A transistor includes a bulk semiconductor substrate, and a first source/drain region in the bulk semiconductor substrate separated from a second source/drain region in the bulk semiconductor substrate by a channel region. A first air gap is defined in the bulk semiconductor substrate under the first source/drain region, and a second air gap is defined in the bulk semiconductor substrate under the second source/drain region. A gate is over the channel region. A spacing between the first air gap and the second air gap is greater than or equal to a length of the channel region such that the first and second air gaps are not under the channel region. The air gaps may have a rectangular cross-sectional shape. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.
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