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    IC STRUCTURE INCLUDING POROUS SEMICONDUCTOR LAYER UNDER TRENCH ISOLATIONS ADJACENT SOURCE/DRAIN REGIONS
    2.
    发明申请
    IC STRUCTURE INCLUDING POROUS SEMICONDUCTOR LAYER UNDER TRENCH ISOLATIONS ADJACENT SOURCE/DRAIN REGIONS 有权

    公开(公告)号：US20230114096A1

    公开(公告)日：2023-04-13

    申请号：US17450186

    申请日：2021-10-07

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Uzma B. Rana ,  Steven M. Shank ,  Anthony K. Stamper

    IPC: H01L29/06 ,  H01Q1/22 ,  H01L29/08

    Abstract: An integrated circuit (IC) structure includes an active device over a bulk semiconductor substrate, and an isolation structure around the active device in the bulk semiconductor substrate. The active device includes a semiconductor layer having a center region, a first end region laterally spaced from the center region by a first trench isolation, a second end region laterally spaced from the center region by a second trench isolation, a gate over the center region, and a source/drain region in each of the first and second end regions. The isolation structure includes: a polycrystalline isolation layer under the active device, a third trench isolation around the active device, and a porous semiconductor layer between the first trench isolation and the polycrystalline isolation layer and between the second trench isolation and the polycrystalline isolation layer.

    IC STRUCTURE INCLUDING POROUS SEMICONDUCTOR LAYER IN BULK SUBSTRATE ADJACENT TRENCH ISOLATION
    3.
    发明公开
    IC STRUCTURE INCLUDING POROUS SEMICONDUCTOR LAYER IN BULK SUBSTRATE ADJACENT TRENCH ISOLATION 审中-公开

    公开(公告)号：US20230215869A1

    公开(公告)日：2023-07-06

    申请号：US17647176

    申请日：2022-01-06

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Uzma B. Rana ,  Steven M. Shank ,  Anthony K. Stamper

    IPC: H01L27/12 ,  H01L21/762

    CPC classification number: H01L27/1207 ,  H01L21/76283

    Abstract: An integrated circuit (IC) structure, a switch and related method, are disclosed. The IC structure includes an active device, e.g., a switch, over a bulk semiconductor substrate, and an isolation structure under the active device in the bulk semiconductor substrate. The isolation structure may include a trench isolation adjacent the active device in the bulk semiconductor substrate, a dielectric layer laterally adjacent the trench isolation and over the active device, and a porous semiconductor layer in the bulk semiconductor substrate under the dielectric layer laterally adjacent the trench isolation. The IC structure employs a lower cost, low resistivity bulk semiconductor substrate rather than a semiconductor-on-insulator (SOI) substrate, yet it has better performance characteristics for RF switches than an SOI substrate.

    TRANSISTOR WITH AIR GAP UNDER RAISED SOURCE/DRAIN REGION IN BULK SEMICONDUCTOR SUBSTRATE
    5.
    发明申请
    TRANSISTOR WITH AIR GAP UNDER RAISED SOURCE/DRAIN REGION IN BULK SEMICONDUCTOR SUBSTRATE 有权

    公开(公告)号：US20230096544A1

    公开(公告)日：2023-03-30

    申请号：US17449336

    申请日：2021-09-29

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Uzma B. Rana ,  Steven M. Shank ,  Anthony K. Stamper

    IPC: H01L29/06 ,  H01L29/08 ,  H01L21/762 ,  H01L21/763

    Abstract: A transistor includes a bulk semiconductor substrate, and first and second raised source/drain regions above the bulk semiconductor substrate. A gate is between the first and second raised source/drain regions. A first dielectric section is beneath the first raised source/drain region in the bulk semiconductor substrate, and a second dielectric section is beneath the second raised source/drain region in the bulk semiconductor substrate. A first air gap is defined in at least the first dielectric section under the first raised source/drain region, and a second air gap is defined in at least the second dielectric section under the second raised source/drain region. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.

    Transistor with air gap under source/drain region in bulk semiconductor substrate
    6.
    发明授权
    Transistor with air gap under source/drain region in bulk semiconductor substrate 有权

    公开(公告)号：US11605710B2

    公开(公告)日：2023-03-14

    申请号：US17155469

    申请日：2021-01-22

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Uzma B. Rana ,  Anthony K. Stamper ,  Steven M. Shank ,  Srikanth Srihari

    IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/04 ,  H01L29/10

    Abstract: A transistor includes a bulk semiconductor substrate, and a first source/drain region in the bulk semiconductor substrate separated from a second source/drain region in the bulk semiconductor substrate by a channel region. A first air gap is defined in the bulk semiconductor substrate under the first source/drain region, and a second air gap is defined in the bulk semiconductor substrate under the second source/drain region. A gate is over the channel region. A spacing between the first air gap and the second air gap is greater than or equal to a length of the channel region such that the first and second air gaps are not under the channel region. The air gaps may have a rectangular cross-sectional shape. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.

    IC structure including porous semiconductor layer in bulk substrate adjacent trench isolation
    8.
    发明授权
    IC structure including porous semiconductor layer in bulk substrate adjacent trench isolation 有权

    公开(公告)号：US12119352B2

    公开(公告)日：2024-10-15

    申请号：US17647176

    申请日：2022-01-06

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Uzma B. Rana ,  Steven M. Shank ,  Anthony K. Stamper

    IPC: H01L27/12 ,  H01L21/762

    CPC classification number: H01L27/1207 ,  H01L21/76283

    Abstract: An integrated circuit (IC) structure, a switch and related method, are disclosed. The IC structure includes an active device, e.g., a switch, over a bulk semiconductor substrate, and an isolation structure under the active device in the bulk semiconductor substrate. The isolation structure may include a trench isolation adjacent the active device in the bulk semiconductor substrate, a dielectric layer laterally adjacent the trench isolation and over the active device, and a porous semiconductor layer in the bulk semiconductor substrate under the dielectric layer laterally adjacent the trench isolation. The IC structure employs a lower cost, low resistivity bulk semiconductor substrate rather than a semiconductor-on-insulator (SOI) substrate, yet it has better performance characteristics for RF switches than an SOI substrate.

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