公开(公告)号：US11887845B2

公开(公告)日：2024-01-30

申请号：US17488883

申请日：2021-09-29

申请人： GLOBALWAFERS JAPAN CO., LTD. ,  TOHOKU UNIVERSITY

发明人： Kazutaka Kamijo ,  Etsuo Fukuda ,  Takashi Ishikawa ,  Koji Izunome ,  Moriya Miyashita ,  Takao Sakamoto ,  Tetsuo Endoh

IPC分类号： H01L21/02 ,  H01L29/66

CPC分类号： H01L21/02255 ,  H01L21/02238 ,  H01L29/66666

摘要： A method for producing a three-dimensional structure, a method for producing a vertical transistor, a vertical transistor wafer, and a vertical transistor substrate, capable of suppressing the emission of Si due to a heat treatment and making an interface between an oxide film and a core mainly consisting of Si relatively smooth include: forming a three-dimensional shape by processing (for example, by etching) a surface layer of a monocrystalline silicon substrate, the surface layer having an oxygen concentration of 1×1017 atoms/cm3 or more; and then forming an oxide film on the surface of the three-dimensional shape by performing a heat treatment. The three-dimensional structure has a shape having projections and recesses in a thickness direction of the silicon substrate, and a height in the thickness direction of the silicon substrate is between 1 nm and 1000 nm, and preferably between 1 nm and 100 nm.