公开(公告)号：US20240355909A1

公开(公告)日：2024-10-24

申请号：US18760217

申请日：2024-07-01

申请人： Micron Technology, Inc.

发明人： Masihhur R. Laskar ,  Jeffery B. Hull ,  Hung-Wei Liu

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H10B51/30

CPC分类号： H01L29/66553 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02345 ,  H01L29/66666 ,  H01L29/6684 ,  H01L29/7827 ,  H01L29/78391 ,  H10B51/30

摘要： Integrated circuitry comprises an electronic component. Insulative silicon dioxide is adjacent the electronic component. The insulative silicon dioxide has at least one of (a) and (b), where: (a): an average concentration of elemental-form H of 0.002 to 0.5 atomic percent; and (b): an average concentration of elemental-form N of 0.005 to 0.3 atomic percent. Other embodiments, including method, are disclosed.

公开(公告)号：US12127386B2

公开(公告)日：2024-10-22

申请号：US17567696

申请日：2022-01-03

申请人： Unisantis Electronics Singapore Pte. Ltd.

发明人： Nozomu Harada

IPC分类号： H10B10/00 ,  H01L21/311 ,  H01L21/768 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H10B10/12 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76816 ,  H01L29/4234 ,  H01L29/66666 ,  H01L29/7827

摘要： P+ layers 32b and 32e that cover the entire top portions of Si pillars 6b and 6e and surround the Si pillars 6b and 6e with an equal width in plan view are formed in a self-aligned manner with the Si pillars 6b and 6e. W layers 33b and 33e are formed on the P+ layers 32b and 32e. A band-shaped contact hole C3 that is partly in contact with regions of the W layers 33b and 33e and that extends in the Y direction is formed. A power supply wiring metal layer Vdd is formed such that the band-shaped contact hole C3 is filled with the power supply wiring metal layer Vdd. In plan view, regions of the W layers 33b and 33e partly protrude outward from the band-shaped contact hole C3.

公开(公告)号：US20240332418A1

公开(公告)日：2024-10-03

申请号：US18448541

申请日：2023-08-11

申请人： Winbond Electronics Corp.

发明人： Yu-Ting CHEN ,  Kai JEN

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7827 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/66666

摘要： A semiconductor device includes: a substrate; a source region disposed on the substrate; a drain region disposed on the source region; and a floating main body region disposed between the source region and the drain region. The floating main body region vertically separates the source region from the drain region. The semiconductor device further includes: a gate region laterally wrapped around the floating main body region; and a gate dielectric located between the floating main body region and the gate region, and insulated the floating main body region from the gate region. A material of the gate dielectric has a negative capacitance feature.

公开(公告)号：US20240321881A1

公开(公告)日：2024-09-26

申请号：US18187989

申请日：2023-03-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yu-Xuan HUANG ,  Chi-Yu LU ,  Shang-Wen CHANG ,  Guan-Lin CHEN ,  Cheng-Chi CHUANG

IPC分类号： H01L27/092 ,  H01L23/528 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/092 ,  H01L23/5286 ,  H01L29/401 ,  H01L29/6653 ,  H01L29/66666 ,  H01L29/7827

摘要： A method includes forming an epitaxial stack including a first sacrificial layer, a channel layer, and a second sacrificial layer over a semiconductor substrate; patterning the epitaxial stack into a fin structure such that opposite first ends of the channel layer are exposed; recessing the opposite first ends of the channel layer; forming first dummy spacers on the recessed opposite first ends of the channel layer; forming an isolation structure in the fin structure; recessing a top surface of the isolation structure to a position lower than a bottom surface of the channel layer, such that opposite second ends of the channel layer are exposed; recessing the opposite second ends of the channel layer; forming second dummy spacers on the recessed opposite second ends of the channel layer; and replacing the first dummy spacers and the second dummy spacers with a metal gate structure.

公开(公告)号：US12100743B2

公开(公告)日：2024-09-24

申请号：US17546072

申请日：2021-12-09

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Ying-Chi Cheng ,  Yu-Jen Huang ,  Shin-Hong Chen

IPC分类号： H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/407 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827

摘要： A semiconductor device and a method for forming the same are provided. The semiconductor device includes a substrate and a gate structure. The gate structure is disposed in the substrate and includes a shielded gate, a control gate, and a plurality of insulating layers. The shielded gate includes a bottom gate and a top gate. The bottom gate includes a step structure consisting of a plurality of electrodes. A width of the electrode is smaller as the electrode is farther away from the top gate, and a width of the top gate is smaller than a width of the electrode closest to the top gate. The control gate is disposed on the shielded gate. A first insulating layer is disposed between the shielded gate and the substrate. A second insulating layer is disposed on the shielded gate. A third insulating layer is disposed between the control gate and the substrate.

公开(公告)号：US12089400B2

公开(公告)日：2024-09-10

申请号：US17452272

申请日：2021-10-26

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Minki Hong

IPC分类号： H01L21/00 ,  H01L29/66 ,  H01L29/78 ,  H01L49/02 ,  H10B12/00

CPC分类号： H10B12/482 ,  H01L28/60 ,  H01L29/66666 ,  H01L29/7827 ,  H10B12/038

摘要： The present disclosure provides a method for forming a semiconductor structure and a semiconductor structure. The method for forming a semiconductor structure includes: providing a substrate, and forming discrete bit line structures on the substrate; forming a first sacrificial layer on the surface of the substrate on the bottoms of gaps of the bit line structures; forming a second sacrificial layer filling the gaps of the discrete bit line structures; patterning the second sacrificial layer and the first sacrificial layer to form openings, the formed openings and the remaining of the second sacrificial layer being arranged alternately in an extension direction of the bit line structures; forming a dielectric layer filling the openings; and, removing the remaining of the first sacrificial layer and the remaining of the second sacrificial layer to form capacitor contact holes, the formed capacitor contact holes and the dielectric layer being arranged alternately.

公开(公告)号：US12080782B2

公开(公告)日：2024-09-03

申请号：US18201868

申请日：2023-05-25

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jun Noh Lee

IPC分类号： H01L29/66 ,  H01L21/311 ,  H01L21/3213 ,  H10B41/27 ,  H10B43/27

CPC分类号： H01L29/66833 ,  H01L21/31105 ,  H01L21/32139 ,  H01L29/66666 ,  H10B41/27 ,  H10B43/27

摘要： A method of forming a semiconductor device includes forming, on a lower structure, a mold structure having interlayer insulating layers and gate layers alternately and repeatedly stacked. Each of the gate layers is formed of a first layer, a second layer, and a third layer sequentially stacked. The first and third layers include a first material, and the second layer includes a second material having an etch selectivity different from an etch selectivity of the first material. A hole formed to pass through the mold structure exposes side surfaces of the interlayer insulating layers and side surfaces of the gate layers. Gate layers exposed by the hole are etched, with an etching speed of the second material differing from an etching speed of the first material, to create recessed regions.

公开(公告)号：US20240290857A1

公开(公告)日：2024-08-29

申请号：US18656251

申请日：2024-05-06

申请人： Huawei Digital Power Technologies Co., Ltd.

发明人： Kimimori HAMADA ,  Fei HU

IPC分类号： H01L29/423 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H02M7/12

CPC分类号： H01L29/4236 ,  H01L29/1608 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7832 ,  H02M7/12

摘要： A semiconductor device includes an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source, and a drain. The epitaxial layer includes a first P-type semiconductor region. A bottom of the trench structure is in contact with the first P-type semiconductor region. The trench structure includes a plurality of first trenches and one second trench. The first trenches extend in a first direction. The second trench and each of the plurality of first trenches are disposed in a cross manner and communicate with each other. The interlayer dielectric layer covers the gate and has a contact hole that extends in a second direction. The source is disposed at the interlayer dielectric layer. The source is in contact with the source region through the contact hole and is connected to the first P-type semiconductor region.

公开(公告)号：US12074220B2

公开(公告)日：2024-08-27

申请号：US17745106

申请日：2022-05-16

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Georgios Vellianitis

IPC分类号： H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/778 ,  H01L21/8234

CPC分类号： H01L29/78618 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/7788 ,  H01L29/78642 ,  H01L29/78696 ,  H01L21/823487

摘要： A semiconductor arrangement and methods of formation are provided. A semiconductor arrangement includes a semiconductor column on a buffer layer over a substrate. The buffer layer comprises a conductive material. Both a first end of the semiconductor column and a bottom contact are connected to a buffer layer such that the first end of the semiconductor column and the bottom contact are connected to one another through the buffer layer, which reduces a contact resistance between the semiconductor column and the bottom contact. A second end of the semiconductor column is connected to a top contact. In some embodiments, the first end of the semiconductor column corresponds to a source or drain of a transistor and the second end corresponds to the drain or source of the transistor.

公开(公告)号：US12068415B2

公开(公告)日：2024-08-20

申请号：US17966817

申请日：2022-10-15

申请人： International Business Machines Corporation

发明人： Kai Zhao ,  Shahab Siddiqui ,  Daniel James Dechene ,  Rishikesh Krishnan ,  Charlotte DeWan Adams

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/78642 ,  H01L21/823418 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

摘要： Epitaxially grow first lower source-drain regions within a substrate. Portions of the substrate adjacent the lower regions are doped to form second lower source-drain regions. An undoped silicon layer is formed over the first and second lower regions. Etch completely through the undoped layer into the first and second lower regions to form fins and to define bottom junctions beneath the fins. The fins and bottom junctions define intermediate cavities. Form lower spacers, gates, and upper spacers in the cavities; form top junctions on outer surfaces of the fins; and form epitaxially grown first upper source-drain regions outward of the upper spacers and opposite the first lower regions. The first upper regions are doped the same as the first lower regions. Form second upper source-drain regions outward of the upper spacers and opposite the second lower regions; these are doped the same as the second lower regions.