DYNAMIC RESET LATENCY
    2.
    发明申请

    公开(公告)号:US20250093921A1

    公开(公告)日:2025-03-20

    申请号:US18559378

    申请日:2022-11-18

    Applicant: Google LLC

    Abstract: A method of resetting a number of functional components in a computing device includes determining a number of cycles required to reset the functional components based on a predetermined voltage controlling a reset synchronizer to run for the determined number of cycles wherein the reset synchronizer controls a reset network connected to the functional components, and wherein the determined number of cycles at a first voltage is different than a determined number of cycles at a second voltage.

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