公开(公告)号：US20210225437A1

公开(公告)日：2021-07-22

申请号：US17221565

申请日：2021-04-02

申请人： GSI Technology, Inc.

发明人： Lee-Lean Shu ,  Eli Ehrman

IPC分类号： G11C11/419 ,  G11C11/418 ,  G11C7/10 ,  G11C7/18 ,  G11C15/04

摘要： A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

公开(公告)号：US20210225436A1

公开(公告)日：2021-07-22

申请号：US17221558

申请日：2021-04-02

申请人： GSI Technology, Inc.

发明人： Lee-Lean Shu ,  Eli Ehrman

IPC分类号： G11C11/419 ,  G11C11/418 ,  G11C7/10 ,  G11C7/18 ,  G11C15/04

摘要： A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

公开(公告)号：US10210935B2

公开(公告)日：2019-02-19

申请号：US15854867

申请日：2017-12-27

申请人： GSI Technology Inc.

发明人： Avidan Akerib ,  Eli Ehrman

IPC分类号： G11C7/10 ,  G11C15/04 ,  G11C8/10 ,  G11C7/18 ,  G06F9/30

摘要： A multiple instruction, multiple data memory device includes a memory array with several sections, one or more multiplexers between the sections and a decoder. Each section has memory cells arranged in rows and columns. The cells in a row are connected by a read enabled word line and by a write enabled word line. The decoder includes a decoder memory array which generally simultaneously activates a plurality of read enabled word lines in several sections, a plurality of write enabled word lines in several sections and one or more multiplexers. The decoder memory array includes several bit lines oriented perpendicularly to and connected to the rows of the memory array. A method of activating in-memory computation using several bit lines of a decoder memory array, connected to rows of the memory array to simultaneously activate several read enabled word lines, several write enabled word lines and one or more multiplexers.

公开(公告)号：US10777262B1

公开(公告)日：2020-09-15

申请号：US16111178

申请日：2018-08-23

申请人： GSI Technology, Inc.

发明人： Bob Haig ,  Eli Ehrman ,  Chao-Hung Chang ,  Mu-Hsiang Huang

IPC分类号： G11C11/419 ,  G11C11/418

摘要： A read register is provided that captures and stores the read result on a read bit line connected to a set of computational memory cells. The read register may be implemented in the set of computational memory cell to enable the logical XOR, logical AND, and/or logical OR accumulation of read results in the read register. The set of computational memory cells with the read register provides a mechanism for performing complex logical functions across multiple computational memory cells connected to the same read bit line.

公开(公告)号：US10770133B1

公开(公告)日：2020-09-08

申请号：US16111182

申请日：2018-08-23

申请人： GSI Technology, Inc.

发明人： Bob Haig ,  Eli Ehrman ,  Patrick Chuang ,  Chao-Hung Chang ,  Mu-Hsiang Huang

IPC分类号： G11C7/00 ,  G11C11/419 ,  G11C11/418

摘要： A read and write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to inhibit writes in selective bit line sections on per-write operation basis to enhance the computational capability of the bl-sects. The read and write data processing apparatus and method also provides a mechanism to inhibit the read bit line pre-charge in selective bit line sections for an extended period of time to save power when pre-charge circuitry is implemented on the read bit line. The read and write data processing apparatus and method also provides a mechanism to inhibit writes to memory cells in selective bl-sects for an extended period of time, to save power.

公开(公告)号：US11670369B2

公开(公告)日：2023-06-06

申请号：US17384873

申请日：2021-07-26

申请人： GSI Technology Inc.

发明人： Avidan Akerib ,  Eli Ehrman

IPC分类号： G11C15/00 ,  G11C15/04

CPC分类号： G11C15/00 ,  G11C15/046

摘要： A method to determine an extreme value of a plurality of data candidates includes storing each data candidate of a plurality of data candidates in a separate column of an associative memory, initializing a row of marker bits by setting each marker bit to a value of 1, computing a subsequent row of marker bits by performing in parallel a Boolean AND operation between a previous row of marker bits and a row of bits of the data candidates, starting with the row of most significant bits of the data candidates, performing a Boolean OR operation between the marker bits in the subsequent row of marker bits to generate a subsequent RSP value, identifying the extreme value from among the plurality of data candidates when there is only one marker bit having a value of 1 in the subsequent row of marker bits coinciding with when said subsequent RSP value is a 1, and if the identifying is false, repeating the computing on a row of next most significant bits, performing and identifying until the identifying is true.

公开(公告)号：US11094374B1

公开(公告)日：2021-08-17

申请号：US16727805

申请日：2019-12-26

申请人： GSI TECHNOLOGY, INC.

发明人： Bob Haig ,  Eli Ehrman ,  Chao-Hung Chang ,  Mu-Hsiang Huang

IPC分类号： G11C11/419 ,  G11C11/418 ,  H03K19/0944

摘要： A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.

公开(公告)号：US10249362B2

公开(公告)日：2019-04-02

申请号：US15709401

申请日：2017-09-19

申请人： GSI Technology, Inc.

发明人： Lee-Lean Shu ,  Eli Ehrman

IPC分类号： G11C11/00 ,  G11C11/419 ,  G11C11/418 ,  G11C7/10 ,  G11C7/18 ,  G11C15/04

摘要： A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

公开(公告)号：US20180158519A1

公开(公告)日：2018-06-07

申请号：US15709399

申请日：2017-09-19

申请人： GSI Technology, Inc.

发明人： Lee-Lean Shu ,  Eli Ehrman

IPC分类号： G11C11/419 ,  G11C11/418

摘要： A memory cell and processing array that has a plurality of memory are capable of performing logic functions, including an exclusive OR (XOR) or an exclusive NOR (XNOR) logic function. The memory cell may have a read port in which the digital data stored in the storage cell of the memory cell is isolated from the read bit line.

公开(公告)号：US09859005B2

公开(公告)日：2018-01-02

申请号：US14594434

申请日：2015-01-12

申请人： GSI Technology Inc.

发明人： Avidan Akerib ,  Eli Ehrman

IPC分类号： G11C15/00 ,  G11C15/04

CPC分类号： G11C15/00 ,  G11C15/046

摘要： Disclosed is a method of selecting a data candidate having a maximum value from a plurality of data candidates stored in columns in a memory array. The method includes computing marker bit values for each row of data in the memory array, and performing a Boolean OR operation on the marker bit values to generate a responder signal value. Also disclosed is a memory device including a memory array of memory cells arranged in rows and columns, and responder signal circuitry to generate a responder signal responsive to positive identification of a data candidate in the memory array.