公开(公告)号：US5295246A

公开(公告)日：1994-03-15

申请号：US91075

申请日：1993-07-13

申请人： Gary Bischoff ,  Paul J. Milot ,  Marc Segre ,  Jeffrey S. Spencer ,  Leslie R. Wilson

发明人： Gary Bischoff ,  Paul J. Milot ,  Marc Segre ,  Jeffrey S. Spencer ,  Leslie R. Wilson

IPC分类号： G06F13/38 ,  G06F5/06 ,  G06F5/10 ,  G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28 ,  G06F5/065 ,  G06F2205/067

摘要： Data transfers between a workstation bus and a graphics adapter bus are handled by a plurality of first-in-first-out (FIFO) buffers, each of which is independently operable to transfer data in a selected direction between the two buses. The FIFOs are accessible either directly by the workstation processor or by means of a DMA operation. Each FIFO is assigned a unique range of addresses in the address space of the workstation processor to permit a workstation process to transfer a block of data to or from a selected FIFO using a single instruction. Workstation writes (reads) to a FIFO are suspended in response to a first status signal indicating that the high (low) threshold for that FIFO has been reached and are restarted in response to a second status signal indicating that the low (high) threshold has been reached. A buffer counter indicating the amount of data in each FIFO is initialized at zero for outbound transfers from the workstation to the adapter or at the maximum buffer count for inbound transfers from the adapter to the workstation. The buffer count is incremented in response to accesses from the workstation side and is decremented in response to accesses from the adapter side, regardless of the direction of transfer.

摘要翻译： 工作站总线和图形适配器总线之间的数据传输由多个先进先出（FIFO）缓冲器来处理，每个缓冲器独立地可操作以在两条总线之间沿所选方向传送数据。 FIFO可以由工作站处理器直接访问，也可以通过DMA操作访问。 在工作站处理器的地址空间中为每个FIFO分配唯一的地址范围，以允许工作站进程使用单个指令将数据块传送到所选择的FIFO或从选定的FIFO传输数据块。 响应于指示该FIFO的高（低）阈值已到达并且响应于指示低（高）阈值具有的第二状态信号而重新启动的第一状态信号，暂停对FIFO的工作站写入（读取） 已经到达 指示每个FIFO中的数据量的缓冲区计数器被初始化为零，用于从工作站到适配器的出站传输或从适配器到工作站的入站传输的最大缓冲区计数。 缓冲器计数响应于来自工作站侧的访问而增加，并且响应于来自适配器侧的访问而递减，而不管传送方向如何。