公开(公告)号：US4827406A

公开(公告)日：1989-05-02

申请号：US34255

申请日：1987-04-01

申请人： Gary Bischoff ,  Dag R. Blokkum ,  Antonio de Leon Penaloza, III ,  David L. Peterson

发明人： Gary Bischoff ,  Dag R. Blokkum ,  Antonio de Leon Penaloza, III ,  David L. Peterson

IPC分类号： G06F12/14 ,  G06F12/02 ,  G06F12/06

CPC分类号： G06F12/0284

摘要： A plurality of processors or intelligent controllers separately utilize discrete pages of a large memory. Within each of these pages a processor can address a plurality of subdivisions or blocks utilizing the processors' address lines. Thus, separate processors having access to this memory and having a limited addressing capability can utilize a plurality of different pages of this memory, within an identical address range, and nevertheless remain confined to separate memory environments established for each of the separate processors. This is accomplished by use of a hardware register to point the separate processors to their assigned pages of the memory and a stored translate table to point to particular blocks of memory within the pages in accordance with a portion of an address generated by the processor accessing the memory.

公开(公告)号：US5295246A

公开(公告)日：1994-03-15

申请号：US91075

申请日：1993-07-13

申请人： Gary Bischoff ,  Paul J. Milot ,  Marc Segre ,  Jeffrey S. Spencer ,  Leslie R. Wilson

发明人： Gary Bischoff ,  Paul J. Milot ,  Marc Segre ,  Jeffrey S. Spencer ,  Leslie R. Wilson

IPC分类号： G06F13/38 ,  G06F5/06 ,  G06F5/10 ,  G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28 ,  G06F5/065 ,  G06F2205/067

摘要： Data transfers between a workstation bus and a graphics adapter bus are handled by a plurality of first-in-first-out (FIFO) buffers, each of which is independently operable to transfer data in a selected direction between the two buses. The FIFOs are accessible either directly by the workstation processor or by means of a DMA operation. Each FIFO is assigned a unique range of addresses in the address space of the workstation processor to permit a workstation process to transfer a block of data to or from a selected FIFO using a single instruction. Workstation writes (reads) to a FIFO are suspended in response to a first status signal indicating that the high (low) threshold for that FIFO has been reached and are restarted in response to a second status signal indicating that the low (high) threshold has been reached. A buffer counter indicating the amount of data in each FIFO is initialized at zero for outbound transfers from the workstation to the adapter or at the maximum buffer count for inbound transfers from the adapter to the workstation. The buffer count is incremented in response to accesses from the workstation side and is decremented in response to accesses from the adapter side, regardless of the direction of transfer.

摘要翻译： 工作站总线和图形适配器总线之间的数据传输由多个先进先出（FIFO）缓冲器来处理，每个缓冲器独立地可操作以在两条总线之间沿所选方向传送数据。 FIFO可以由工作站处理器直接访问，也可以通过DMA操作访问。 在工作站处理器的地址空间中为每个FIFO分配唯一的地址范围，以允许工作站进程使用单个指令将数据块传送到所选择的FIFO或从选定的FIFO传输数据块。 响应于指示该FIFO的高（低）阈值已到达并且响应于指示低（高）阈值具有的第二状态信号而重新启动的第一状态信号，暂停对FIFO的工作站写入（读取） 已经到达 指示每个FIFO中的数据量的缓冲区计数器被初始化为零，用于从工作站到适配器的出站传输或从适配器到工作站的入站传输的最大缓冲区计数。 缓冲器计数响应于来自工作站侧的访问而增加，并且响应于来自适配器侧的访问而递减，而不管传送方向如何。

公开(公告)号：US4703598A

公开(公告)日：1987-11-03

申请号：US856711

申请日：1986-04-28

申请人： Harold R. Wilson ,  Gary Ottenjan ,  Gary Bischoff

发明人： Harold R. Wilson ,  Gary Ottenjan ,  Gary Bischoff

IPC分类号： E04B2/74 ,  E06B3/54 ,  E06B3/62 ,  E04H1/12

CPC分类号： E04B2/7409 ,  E06B3/62 ,  E06B2003/5463 ,  E06B2003/6208 ,  E06B2003/6244 ,  E06B2003/6252 ,  E06B2003/6258

摘要： A privacy wall for joining a floor and ceiling, which wall includes a lower panel projecting upwardly from the floor, and a privacy panel extending vertically between the ceiling and the upper edge of the lower panel. The privacy panel has upper and lower edges supported within retainers confined within recesses defined by support tracks. The upper and lower retainers are identical but reversely vertically oriented relative to the respective recesses. Each retainer includes a central base wall and pairs of first and second legs projecting outwardly in opposite directions to define first and second oppositely oriented channels which accommodate the edge of the privacy panel therein. The first legs are short and inclined inwardly so that the lower edge of the panel can be sealingly accommodated therebetween. The second legs are of greater length and have sideward flanges adjacent the ends thereof. The upper retainer is oriented with the second legs projecting downwardly, with the deflected second legs being sealingly engaged with opposite sides of the privacy panel.

摘要翻译： 用于连接地板和天花板的隐私墙，该墙包括从地板向上突出的下板，以及在天花板和下板的上边缘之间垂直延伸的隐私板。 隐私面板具有被限定在由支撑轨道限定的凹部内的保持器内支撑的上边缘和下边缘。 上部和下部保持器相对于相应的凹部相同但相反地垂直定向。 每个保持器包括中心底壁和一对在相反方向向外突出的第一和第二腿，以限定第一和第二相对定向的通道，其容纳其中的隐私面板的边缘。 第一腿短而向内倾斜，使得面板的下边缘可以密封地容纳在它们之间。 第二腿具有更大的长度并且具有邻近其端部的侧向凸缘。 上保持器定向成使第二腿向下突出，偏转的第二腿与隐私面板的相对侧密封地接合。