公开(公告)号：US06192452B1

公开(公告)日：2001-02-20

申请号：US09259378

申请日：1999-02-26

申请人： John Peyton Bannister ,  Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

发明人： John Peyton Bannister ,  Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

IPC分类号： G06F1200

CPC分类号： G06F12/0813

摘要： A method for avoiding data loss due to cancelled transactions within a non-uniform memory access (NUMA) data processing system is disclosed. A NUMA data processing system includes a node interconnect to which at least a first node and a second node are coupled. The first and the second nodes each includes a local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and a node interconnect. The node controller detects certain situations which, due to the nature of a NUMA data processing system, can lead to data loss. These situations share the common feature that a node controller ends up with the only copy of a modified cache line and the original transaction that requested the modified cache line may not be issued again with the same tag or may not be issued again at all. The node controller corrects these situations by issuing its own write transaction to the system memory for that modified cache line using its own tag, and then providing the data the modified cache line is holding. This ensures that the modified data will be written to the system memory.

摘要翻译： 公开了一种用于避免由于在非均匀存储器访问（NUMA）数据处理系统中被取消的事务而导致的数据丢失的方法。 NUMA数据处理系统包括至少第一节点和第二节点耦合到的节点互连。 第一和第二节点各自包括本地互连，耦合到本地互连的系统存储器和插入在本地互连和节点互连之间的节点控制器。 节点控制器检测某些情况，由于NUMA数据处理系统的性质，可能导致数据丢失。 这些情况共享了节点控制器以修改的高速缓存行的唯一副本结束的共同特征，并且请求修改的高速缓存行的原始事务可能不会以相同的标签重新发出，也可能根本不再发出。 节点控制器通过使用其自己的标签向修改的高速缓存行发出自己的写入事务来修正这些情况，然后提供修改后的高速缓存行正在保存的数据。 这样可以确保将修改后的数据写入系统内存。

公开(公告)号：US6081874A

公开(公告)日：2000-06-27

申请号：US162828

申请日：1998-09-29

申请人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

发明人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

IPC分类号： G06F15/163 ,  G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0813

摘要： A non-uniform memory access (NUMA) data processing system includes a node interconnect to which at least a first processing node and a second processing node are coupled. The first and the second processing nodes each include a local interconnect, a processor coupled to the local interconnect, a system memory coupled to the local interconnect, and a node controller interposed between the local interconnect and the node interconnect. In order to reduce communication latency, the node controller of the first processing node speculatively transmits request transactions received from the local interconnect of the first processing node to the second processing node via the node interconnect. In one embodiment, the node controller of the first processing node subsequently transmits a status signal to the node controller of the second processing node in order to indicate how the request transaction should be processed at the second processing node.

摘要翻译： 非均匀存储器访问（NUMA）数据处理系统包括至少第一处理节点和第二处理节点耦合到的节点互连。 第一处理节点和第二处理节点各自包括本地互连，耦合到本地互连的处理器，耦合到本地互连的系统存储器，以及插入在本地互连和节点互连之间的节点控制器。 为了减少通信延迟，第一处理节点的节点控制器通过节点互连将从第一处理节点的本地互连接收的请求事务推测发送到第二处理节点。 在一个实施例中，第一处理节点的节点控制器随后将状态信号发送到第二处理节点的节点控制器，以便指示如何在第二处理节点处理请求事务。

公开(公告)号：US6067611A

公开(公告)日：2000-05-23

申请号：US106945

申请日：1998-06-30

申请人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco ,  Richard Nicholas Iachetta

发明人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco ,  Richard Nicholas Iachetta

IPC分类号： G06F15/177 ,  G06F12/08 ,  G06F13/38 ,  G06F15/17 ,  G06F15/16

CPC分类号： G06F15/17

摘要： A non-uniform memory access (NUMA) computer system includes an interconnect to which multiple processing nodes (including first, second, and third processing nodes) are coupled. Each of the first, second, and third processing nodes includes at least one processor and a local system memory. The NUMA computer system further includes a transaction buffer, coupled to the interconnect, that stores communication transactions transmitted on the interconnect that are both initiated by and targeted at a processing node other than the third processing node. In response to a determination that a particular communication transaction originally targeting another processing node should be processed by the third processing node, buffer control logic coupled to the transaction buffer causes the particular communication transaction to be retrieved from the transaction buffer and processed by the third processing node. In one embodiment, the interconnect includes a broadcast fabric, and the transaction buffer and buffer control logic form a portion of the third processing node.

摘要翻译： 不均匀存储器访问（NUMA）计算机系统包括多个处理节点（包括第一，第二和第三处理节点）耦合到的互连。 第一，第二和第三处理节点中的每一个包括至少一个处理器和本地系统存储器。 NUMA计算机系统还包括耦合到互连的事务缓冲器，其存储在互连上发送的通信事务，所述通信事务由第三处理节点以外的处理节点发起和定向。 响应于原先针对另一个处理节点的特定通信交易应该由第三处理节点处理的响应，耦合到事务缓冲器的缓冲器控制逻辑使得从事务缓冲器检索特定的通信事务并且通过第三处理进行处理 节点。 在一个实施例中，互连包括广播结构，并且事务缓冲器和缓冲器控制逻辑形成第三处理节点的一部分。

公开(公告)号：US06178472B1

公开(公告)日：2001-01-23

申请号：US09097331

申请日：1998-06-15

申请人： Gary Dale Carpenter ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

发明人： Gary Dale Carpenter ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

IPC分类号： G06F1312

CPC分类号： G06F7/78

摘要： A queue includes a data multiplexer having an output and at least two inputs and a plurality of data latches. The data latches include at least a first data latch and a second data latch, which each have a data input and a data output. The data output of the first data latch is coupled to a first input of the data multiplexer, and the output of the data multiplexer is coupled to the data input of the second data latch. A data value to be stored in the queue is received at a second input to the data multiplexer. In response to one or more control signals, the data value is latched into at least one of the first and second data latches, thereby storing the data value in the queue. Depending upon the design of the control logic, the queue can implement either first in, first out (FIFO) or last in, first out (LIFO) behavior.

摘要翻译： 队列包括具有输出和至少两个输入和多个数据锁存器的数据多路复用器。 数据锁存器至少包括第一数据锁存器和第二数据锁存器，每个锁存器具有数据输入和数据输出。 第一数据锁存器的数据输出耦合到数据多路复用器的第一输入端，并且数据多路复用器的输出耦合到第二数据锁存器的数据输入端。 要存储在队列中的数据值在第二输入处被接收到数据多路复用器。 响应于一个或多个控制信号，数据值被锁存到第一和第二数据锁存器中的至少一个中，从而将数据值存储在队列中。 根据控制逻辑的设计，队列可以先进先出（FIFO）或最后进先出（LIFO）行为。

公开(公告)号：US6085293A

公开(公告)日：2000-07-04

申请号：US135283

申请日：1998-08-17

申请人： Gary Dale Carpenter ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

发明人： Gary Dale Carpenter ,  David Brian Glasco ,  Richard Nicholas Iachetta, Jr.

IPC分类号： G06F15/16 ,  G06F12/08 ,  G06F12/16

CPC分类号： G06F12/0813 ,  G06F2212/2542

摘要： A non-uniform memory access (NUMA) computer system includes a node interconnect and a plurality of processing nodes that each contain at least one processor, a local interconnect, a local system memory, and a node controller coupled to both a respective local interconnect and the node interconnect. According to the method of the present invention, a communication transaction is transmitted on the node interconnect from a local processing node to a remote processing node. In response to receipt of the communication transaction by the remote processing node, a response including a coherency response field is transmitted on the node interconnect from the remote processing node to the local processing node. In response to receipt of the response at the local processing node, a request is issued on the local interconnect of the local processing node concurrently with a determination of a coherency response indicated by the coherency response field.

摘要翻译： 不均匀存储器访问（NUMA）计算机系统包括节点互连和多个处理节点，每个处理节点包含至少一个处理器，本地互连，本地系统存储器和耦合到相应的本地互连和 节点互连。 根据本发明的方法，在节点互连上从本地处理节点向远程处理节点发送通信事务。 响应于远程处理节点接收到通信事务，在节点互连上从远程处理节点向本地处理节点发送包括一致性响应字段的响应。 响应于在本地处理节点处的响应的接收，在本地处理节点的本地互连上同时确定由相关性响应字段指示的一致性响应的请求。

公开(公告)号：US06269428B1

公开(公告)日：2001-07-31

申请号：US09259367

申请日：1999-02-26

申请人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

发明人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

IPC分类号： G06F1200

CPC分类号： G06F12/0828 ,  G06F12/0813

摘要： A method for avoiding livelocks due to colliding invalidating transactions within a non-uniform memory access system is disclosed. A NUMA computer system includes at least two nodes coupled to an interconnect. Each of the two nodes includes a local system memory. In response to a request by a processor of a first node to invalidate a remote copy of a cache line also stored within its cache memory at substantially the same time when a processor of a second node is also requesting to invalidate said cache line, one of the two requests is allowed to complete. The allowed request is the first request to complete without retry at the point of coherency, typically the home node. Subsequently, the other one of the two requests is permitted to complete.

摘要翻译： 公开了一种用于避免由于在非均匀存储器访问系统内的无效事务的冲突而导致的活动锁定的方法。 NUMA计算机系统包括耦合到互连的至少两个节点。 两个节点中的每一个包括本地系统存储器。 响应于第一节点的处理器在第二节点的处理器也要求使所述高速缓存行无效的基本上同时存储在其高速缓冲存储器中的高速缓存行的远端副本的请求时， 这两个请求被允许完成。 允许的请求是第一个完成的请求，而不是在一致性的时候重试，通常是家庭节点。 随后，两个请求中的另一个被允许完成。

公开(公告)号：US06275907B1

公开(公告)日：2001-08-14

申请号：US09184395

申请日：1998-11-02

申请人： Yoanna Baumgartner ,  Gary Dale Carpenter ,  Mark Edward Dean ,  Anna Elman ,  James Stephen Fields, Jr. ,  David Brian Glasco

发明人： Yoanna Baumgartner ,  Gary Dale Carpenter ,  Mark Edward Dean ,  Anna Elman ,  James Stephen Fields, Jr. ,  David Brian Glasco

IPC分类号： G06F1208

CPC分类号： G06F12/0828 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087

摘要： A non-uniform memory access (NUMA) computer system includes a plurality of processing nodes coupled to a node interconnect. The plurality of processing nodes include at least a remote processing node, which contains a processor having an associated cache hierarchy, and a home processing node. The home processing node includes a shared system memory containing a plurality of memory granules and a coherence directory that indicates possible coherence states of copies of memory granules among the plurality of memory granules that are stored within at least one processing node other than the home processing node. If the processor within the remote processing node has a reservation for a memory granule among the plurality of memory granules that is not resident within the associated cache hierarchy, the coherence directory associates the memory granule with a coherence state indicating that the reserved memory granule may possibly be held non-exclusively at the remote processing node. In this manner, the coherence mechanism can be utilized to manage processor reservations even in cases in which a reserving processor's cache hierarchy does not hold a copy of the reserved memory granule.

摘要翻译： 非均匀存储器访问（NUMA）计算机系统包括耦合到节点互连的多个处理节点。 多个处理节点至少包括一个远程处理节点，其包含具有相关联的高速缓存层级的处理器和家庭处理节点。 家庭处理节点包括包含多个存储器颗粒的共享系统存储器和指示存储在除家庭处理节点之外的至少一个处理节点中的多个存储器颗粒中的存储器颗粒的副本的可能的相干状态的一致性目录 。 如果远程处理节点内的处理器对于不驻留在相关联的高速缓存层级中的多个存储器颗粒中的存储器颗粒进行预留，则相干目录将存储器颗粒与指示保留的存储器颗粒可能的相干状态相关联 不排他地保存在远程处理节点。 以这种方式，即使在保留处理器的高速缓存层级不保留预留的存储器颗粒的副本的情况下，也可以利用相干机制来管理处理器预留。

公开(公告)号：US06266743B1

公开(公告)日：2001-07-24

申请号：US09259365

申请日：1999-02-26

申请人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

发明人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

IPC分类号： G06F1200

CPC分类号： G06F12/082 ,  G06F12/12

摘要： A method and system for providing an eviction protocol within a non-uniform memory access (NUMA) computer system are disclosed. A NUMA computer system includes at least two nodes coupled to an interconnect. Each of the two nodes includes a local system memory. In response to a request for evicting an entry from a sparse directory, an non-intervention writeback request is sent to a node having the modified cache line when the entry is associated with a modified cache line. After the data from the modified cache line has been written back to a local system memory of the node, the entry can then be evicted from the sparse directory. If the entry is associated with a shared line, an invalidation request is sent to all nodes that the directory entry indicates may hold a copy of the line. Once all invalidations have been acknowledged, the entry can be evicted from the sparse directory.

摘要翻译： 公开了一种用于在非均匀存储器访问（NUMA）计算机系统内提供逐出协议的方法和系统。 NUMA计算机系统包括耦合到互连的至少两个节点。 两个节点中的每一个包括本地系统存储器。 响应于从稀疏目录驱逐条目的请求，当该条目与修改的高速缓存行相关联时，不干预回写请求被发送到具有修改的高速缓存行的节点。 在来自修改的高速缓存行的数据已经被写回节点的本地系统存储器之后，该条目然后可以从稀疏目录中被逐出。 如果条目与共享线路相关联，则将无效请求发送到目录条目指示的所有节点可能保存该线路的副本。 一旦所有的无效被确认，该条目可以从稀疏目录中被逐出。

公开(公告)号：US06226718B1

公开(公告)日：2001-05-01

申请号：US09259379

申请日：1999-02-26

申请人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

发明人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

IPC分类号： G06F1202

CPC分类号： G06F12/0813

摘要： A method for avoiding livelocks due to stale exclusive/modified directory entries within a non-uniform memory access (NUMA) computer system is disclosed. A NUMA computer system includes at least two nodes coupled to an interconnect. Each of the two nodes includes a local system memory. In response to an attempt by a processor of a first node to read a cache line at substantially the same time as a processor of a second node attempts to access the same cache line, wherein the cache line has been silently cast out from a cache memory within the second node even though a coherency directory within the node still indicates the cache line is held exclusively in the second node, the processor of the second node is allowed to access the cache line only if the second node is an owning node of the cache line. The processor of the first node is then allowed to access the cache line.

摘要翻译： 公开了一种用于避免由于在非均匀存储器存取（NUMA）计算机系统内的过时的独占/修改的目录条目引起的活动锁定的方法。 NUMA计算机系统包括耦合到互连的至少两个节点。 两个节点中的每一个包括本地系统存储器。 响应于第一节点的处理器尝试在与第二节点的处理器尝试访问相同的高速缓存行的基本上相同的时间读取高速缓存行，其中高速缓存行已经从高速缓冲存储器 即使在节点内的一致性目录仍然指示高速缓存行仅在第二节点中被保留在第二节点内，则仅当第二节点是高速缓存的所有节点时才允许第二节点的处理器访问高速缓存行 线。 然后允许第一个节点的处理器访问高速缓存行。

公开(公告)号：US6115804A

公开(公告)日：2000-09-05

申请号：US248503

申请日：1999-02-10

申请人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

发明人： Gary Dale Carpenter ,  Mark Edward Dean ,  David Brian Glasco

IPC分类号： G06F12/08 ,  G06F15/00

CPC分类号： G06F12/0813

摘要： A non-uniform memory access (NUMA) computer system includes first and second processing nodes that are each coupled to a node interconnect. The first processing node includes a system memory and first and second processors that each have a respective one of first and second cache hierarchies, which are coupled for communication by a local interconnect. The second processing node includes at least a system memory and a third processor having a third cache hierarchy. The first cache hierarchy and the third cache hierarchy are permitted to concurrently store an unmodified copy of a particular cache line in a Recent coherency state from which the copy of the particular cache line can be sourced by shared intervention. In response to a request for the particular cache line by the second cache hierarchy, the first cache hierarchy sources a copy of the particular cache line to the second cache hierarchy by shared intervention utilizing communication on only the local interconnect and without communication on the node interconnect.

摘要翻译： 非均匀存储器访问（NUMA）计算机系统包括第一和第二处理节点，每个处理节点都耦合到节点互连。 第一处理节点包括系统存储器和第一和第二处理器，每个处理器具有第一和第二高速缓存层级中的相应一个，其被耦合用于通过局部互连进行通信。 第二处理节点至少包括系统存储器和具有第三高速缓存层级的第三处理器。 允许第一高速缓存层级和第三高速缓存层次结构将特定高速缓存行的未修改副本并入存储在最近的一致性状态中，通过共享干预可以从特定高速缓存行的副本提供特定高速缓存行的副本。 响应于通过第二高速缓存层次结构对特定高速缓存线的请求，第一高速缓存层级通过仅在局部互连上的通信的共享干预将特定高速缓存行的副本提供给第二高速缓存层级，并且在节点互连上没有通信 。