公开(公告)号：US20070061124A1

公开(公告)日：2007-03-15

申请号：US11225689

申请日：2005-09-12

申请人： Gary Van Huben ,  Edward Kaminski ,  Elspeth Huston

发明人： Gary Van Huben ,  Edward Kaminski ,  Elspeth Huston

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： Disclosed is a method for constructing a Hybrid Cycle Simulation model comprising Compiled Data Units (CDUs) for use in design verification. The simulation model may contain a plurality of 1-cycle CDUs, optimized for simulation throughput, and 2-cycle CDUs, optimized for simulation accuracy, or a mixture thereof. Utilizing a netlist tool extracting hierarchical design source components for use, the contruction checks that all inputs and outputs of any hierarchical design source components bind, and employs Object Traversal Directives for incorporating the selected CDUs into the simulation model. A data management method is used for tracking the validity of the components in the model. Additionally, a software entity (FACDDR) permits high bandwidth simulation of design components normally requiring cycle accurate simulation. FACDDR provides linkages for standard logic elements for abstracting one or more design interface components out of a cycle simulation environment and design interface emulation of an interface which interacts with a cycle simulation model through an API to extract present value of driving side signals of an interface and to set the cycle simulation model on the receiving side.

摘要翻译： 公开了一种用于构建用于设计验证的编译数据单元（CDU）的混合周期模拟模型的方法。 模拟模型可以包含针对模拟吞吐量优化的多个1周期CDU，以及针对模拟精度优化的2周期CDU或其混合。 利用网表工具提取分层设计源组件进行使用，该方案检查所有分层设计源组件的所有输入和输出是否绑定，并使用对象遍历指令将所选择的CDU合并到仿真模型中。 数据管理方法用于跟踪模型中组件的有效性。 另外，一个软件实体（FACDDR）允许设计组件的高带宽仿真，通常需要循环精确的模拟。 FACDDR为标准逻辑元件提供链接，用于从循环模拟环境中抽取一个或多个设计接口组件，并通过API与循环模拟模型交互的界面的设计界面仿真，以提取接口的驱动侧信号的当前值， 在接收侧设置循环模拟模型。

公开(公告)号：US20060184905A1

公开(公告)日：2006-08-17

申请号：US11055863

申请日：2005-02-11

申请人： Michael Floyd ,  Joshua Friedrich ,  Elspeth Huston ,  Wolfgang Roesner ,  Rick Weiss

发明人： Michael Floyd ,  Joshua Friedrich ,  Elspeth Huston ,  Wolfgang Roesner ,  Rick Weiss

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： A method, an apparatus and computer instructions are provided for specifying multiple voltage domains of a signal and macros in a processor chip and validating physical implementation and interconnections of the signal and macros. A set of attributes is provided for designs to define multiple voltage domains of a signal and macros in a processor chip. A first validation mechanism is then provided to validate that no electrical or logical errors created by logical connections between macros as defined by the set of attributes. A translation mechanism is provided to translate logical voltage description to a physical netlist for designers to connect powers to macros and signals. A second validation mechanism is provided to validate physical implementation adhere to designers' intent according to the set of attributes defined in the logical design.

摘要翻译： 提供了一种用于指定处理器芯片中的信号和宏的多个电压域并验证信号和宏的物理实现和互连的方法，装置和计算机指令。 提供了一组属性，用于设计以定义处理器芯片中的信号和宏的多个电压域。 然后提供第一个验证机制来验证由该属性集所定义的宏之间的逻辑连接所产生的电或逻辑错误。 提供了一种翻译机制，用于将逻辑电压描述转换为物理网表，供设计师将功能连接到宏和信号。 提供了第二个验证机制，以根据逻辑设计中定义的属性集来验证物理实现符合设计者的意图。