公开(公告)号：US20060184905A1

公开(公告)日：2006-08-17

申请号：US11055863

申请日：2005-02-11

申请人： Michael Floyd ,  Joshua Friedrich ,  Elspeth Huston ,  Wolfgang Roesner ,  Rick Weiss

发明人： Michael Floyd ,  Joshua Friedrich ,  Elspeth Huston ,  Wolfgang Roesner ,  Rick Weiss

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： A method, an apparatus and computer instructions are provided for specifying multiple voltage domains of a signal and macros in a processor chip and validating physical implementation and interconnections of the signal and macros. A set of attributes is provided for designs to define multiple voltage domains of a signal and macros in a processor chip. A first validation mechanism is then provided to validate that no electrical or logical errors created by logical connections between macros as defined by the set of attributes. A translation mechanism is provided to translate logical voltage description to a physical netlist for designers to connect powers to macros and signals. A second validation mechanism is provided to validate physical implementation adhere to designers' intent according to the set of attributes defined in the logical design.

摘要翻译： 提供了一种用于指定处理器芯片中的信号和宏的多个电压域并验证信号和宏的物理实现和互连的方法，装置和计算机指令。 提供了一组属性，用于设计以定义处理器芯片中的信号和宏的多个电压域。 然后提供第一个验证机制来验证由该属性集所定义的宏之间的逻辑连接所产生的电或逻辑错误。 提供了一种翻译机制，用于将逻辑电压描述转换为物理网表，供设计师将功能连接到宏和信号。 提供了第二个验证机制，以根据逻辑设计中定义的属性集来验证物理实现符合设计者的意图。

公开(公告)号：US07877717B2

公开(公告)日：2011-01-25

申请号：US11874620

申请日：2007-10-18

申请人： Bing-Lun Chu ,  Yee Ja ,  Bradley S. Nelson ,  Wolfgang Roesner

发明人： Bing-Lun Chu ,  Yee Ja ,  Bradley S. Nelson ,  Wolfgang Roesner

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5022 ,  G06F17/5031

摘要： Mechanisms for accurately modeling an asynchronous interface using expanded logic elements are provided. With these mechanisms, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration whether or not the primitive logic elements themselves may be experiencing a switching or glitch hazard and whether or not the inputs to the primitive logic elements may be based on a switching or glitch hazard from another primitive logic element in the asynchronous interface logic. These expanded logic elements are used in an integrated circuit design to replace the original primitive logic elements in the design. The asynchronous interface may then be simulated with the expanded logic elements providing outputs indicative of whether the actual data output of the expanded logic elements is deterministic or not.

摘要翻译： 提供了使用扩展逻辑元件对异步接口进行精确建模的机制。 利用这些机制，将异步接口的逻辑简化为原始逻辑元件。 这些原始逻辑元件通过本发明的机制来扩展，以考虑原语逻辑元件本身是否可能经历切换或毛刺危险，以及基本逻辑元件的输入是否可以基于切换 或异步接口逻辑中另一原始逻辑元件的故障危险。 这些扩展的逻辑元件用于集成电路设计中以替代设计中的原始原始逻辑元件。 然后可以用扩展的逻辑元件来模拟异步接口，该逻辑元件提供指示扩展的逻辑元件的实际数据输出是否是确定性的输出。

公开(公告)号：US07838925B2

公开(公告)日：2010-11-23

申请号：US12173524

申请日：2008-07-15

申请人： Wolfgang Roesner ,  Franz Hofmann

发明人： Wolfgang Roesner ,  Franz Hofmann

IPC分类号： H01L29/732

CPC分类号： H01L29/7827 ,  H01L21/2255 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10876 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/66734 ,  H01L29/7813

摘要： An integrated circuit including a vertical transistor and method of manufacturing. In one embodiment a vertical transistor is formed in a pillar of a semiconductor substrate. A buried conductive line is separated from the semiconductor substrate by a first insulating layer in a first portion and is electrically coupled to a buried source/drain region of the vertical transistor through a contact structure. A second insulating layer is arranged above and adjacent to the contact structure. At least one of the first and second insulating layers includes a dopant. A doped region is formed in the semiconductor substrate at an interface to the at least one insulating layer. The doped region has a dopant concentration higher than a substrate dopant concentration.

摘要翻译： 一种包括垂直晶体管和制造方法的集成电路。 在一个实施例中，垂直晶体管形成在半导体衬底的柱中。 埋入导线通过第一部分中的第一绝缘层与半导体衬底分离，并通过接触结构电耦合到垂直晶体管的掩埋源/漏区。 第二绝缘层布置在接触结构的上方并与之相邻。 第一和第二绝缘层中的至少一个包括掺杂剂。 掺杂区域形成在半导体衬底中与至少一个绝缘层的界面处。 掺杂区域的掺杂浓度高于衬底掺杂剂浓度。

公开(公告)号：US07829892B2

公开(公告)日：2010-11-09

申请号：US11926653

申请日：2007-10-29

申请人： Richard Johannes Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Roesner ,  Till Schloesser ,  Michael Specht

发明人： Richard Johannes Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Roesner ,  Till Schloesser ,  Michael Specht

IPC分类号： H01L29/12

CPC分类号： H01L27/10823 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10891 ,  H01L29/7851

摘要： An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.

摘要翻译： 公开了一种包括栅电极的集成电路。 一个实施例提供一种晶体管，其包括第一源极/漏极电极和第二源极/漏极电极。 在半导体衬底中的第一和第二源极/漏极之间布置有沟道。 栅电极被布置在沟道层附近并且与沟道层电绝缘。 半导体基板电极设置在后侧。 栅极电极将沟道层包围至少两个相对的侧面。

公开(公告)号：US07805695B2

公开(公告)日：2010-09-28

申请号：US11829447

申请日：2007-07-27

申请人： Wolfgang Roesner ,  Derek Edward Williams

发明人： Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F17/50 ,  G06F17/00 ,  G09G5/00

CPC分类号： G06F17/5022

摘要： Within a display device, a respective one of a plurality of design graphical representations is displayed for each of a plurality of hierarchically arranged design entity instances within a simulated system. The design entity instances include a particular design entity instance containing a latch that is represented by a particular design graphical representation. A configuration entity instance associated with the particular design entity is identified within a configuration database associated with the simulated system. The configuration entity instance has a plurality of different settings that each reflects a value of the latch. Within the display device, a configuration graphical representation of the configuration entity instance is presented in association with the particular design graphical representation corresponding to the particular design entity instance. In addition, a current setting of the configuration entity instance is presented concurrently with the configuration graphical representation.

摘要翻译： 在显示装置内，为模拟系统内的多个分层布置的设计实体实例中的每一个显示多个设计图形表示中的相应一个。 设计实体实例包括包含由特定设计图形表示表示的锁存器的特定设计实体实例。 在与模拟系统相关联的配置数据库中识别与特定设计实体相关联的配置实体实例。 配置实体实例具有多个不同的设置，每个设置反映锁存器的值。 在显示设备内，与对应于特定设计实体实例的特定设计图形表示相关联地呈现配置实体实例的配置图形表示。 此外，配置实体实例的当前设置与配置图形表示同时呈现。

公开(公告)号：US07774724B2

公开(公告)日：2010-08-10

申请号：US12102116

申请日：2008-04-14

申请人： Bryan R. Hunt ,  Wolfgang Roesner ,  Robert J. Shadowen ,  Derek E. Williams

发明人： Bryan R. Hunt ,  Wolfgang Roesner ,  Robert J. Shadowen ,  Derek E. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： In a method of data processing, a database defines a Dial entity and at least one instance of the Dial entity. Each instance of the Dial entity has an input having a plurality of different possible input values and one or more outputs, and each of the plurality of different possible input values has a different associated output value set for the one or more outputs. Each instance of the Dial entity determines a value of at least one of a plurality of configuration latches in a digital system separate from the database. The database also associates with the Dial entity at least one set of biasing weights that, when applied, determines a probability of each instance of the Dial entity having particular ones of the plurality of different possible input values. In response to a call to set the plurality of configuration latches, the database is accessed to apply the at least one set of biasing weights to select one of the plurality of different possible input values for the at least one instance of the Dial entity. The plurality of configuration latches in the digital system are set based upon the output value set for the one or more outputs of the at least one instance of the Dial entity.

摘要翻译： 在数据处理的方法中，数据库定义了Dial实体和Dial实体的至少一个实例。 Dial实体的每个实例具有具有多个不同可能输入值和一个或多个输出的输入，并且多个不同可能输入值中的每一个具有为一个或多个输出设置的不同的相关输出值。 Dial实体的每个实例确定与数据库分离的数字系统中的多个配置锁存器中的至少一个的值。 所述数据库还将所述至少一组偏置权重与所述拨号实体相关联，所述偏置权重在被应用时确定具有所述多个不同可能输入值中的特定个体的所述拨号实体的每个实例的概率。 响应于设置多个配置锁存器的呼叫，访问数据库以应用至少一组偏置权重以选择Dial实体的至少一个实例的多个不同可能输入值中的一个。 基于为Dial实体的至少一个实例的一个或多个输出设置的输出值来设置数字系统中的多个配置锁存器。

公开(公告)号：US07765513B2

公开(公告)日：2010-07-27

申请号：US11762597

申请日：2007-06-13

申请人： Wolfgang Roesner ,  Derek Edward Williams

发明人： Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains a latch having a respective plurality of different possible latch values. With one or more statements in one or more files, a configuration entity is associated with the latch. The configuration entity has a plurality of different settings and each setting reflects which of the plurality of different possible values is loaded in the associated latch. A controlling value set for at least one instance of the configuration entity is also defined in one or more files. The controlling value set indicates at least one controlling value for which presentation of a current setting of the configuration entity instance is restricted. Thereafter, in response to a request to present at least a partial state of the digital system, a current setting of the configuration entity instance is excluded from presentation by reference to a configuration database indicating the controlling value set.

摘要翻译： 在至少一个硬件定义语言（HDL）文件中，指定包含数字系统功能部分的至少一个设计实体。 设计实体逻辑地包含具有相应多个不同可能锁存值的锁存器。 在一个或多个文件中使用一个或多个语句，配置实体与锁存器相关联。 配置实体具有多个不同的设置，并且每个设置反映多个不同的可能值中的哪一个加载到相关联的锁存器中。 对于配置实体的至少一个实例设置的控制值也被定义在一个或多个文件中。 控制值集合指示限制配置实体的当前设置的呈现的至少一个控制值。 此后，响应于呈现数字系统的至少部分状态的请求，通过参考指示控制值集合的配置数据库将配置实体实例的当前设置排除在呈现之外。

公开(公告)号：US07752026B2

公开(公告)日：2010-07-06

申请号：US12049680

申请日：2008-03-17

申请人： Carol Ivash Gabele ,  Wolfgang Roesner ,  Derek Edward Williams

发明人： Carol Ivash Gabele ,  Wolfgang Roesner ,  Derek Edward Williams

IPC分类号： G06F17/50 ,  G06F9/45 ,  G06F11/30

CPC分类号： G06F17/5022

摘要： A system and computer program product for providing centralized access to count event information from testing of a hardware simulation model within a batch simulation farm which includes simulation clients and an instrumentation server. Count event data for said hardware simulation model is received by the instrumentation server from one or more simulation clients. A first and a second counter report are generated for the hardware simulation model, in which the first and second counter reports are derived from the count event data received by the instrumentation server. The first counter report is compared to the second counter report, and responsive to this comparison, a counter difference report is generated within the instrumentation server that conveys count event trends associated with the simulation model under different simulation testcases.

摘要翻译： 一种系统和计算机程序产品，用于通过在包含模拟客户端和仪器服务器的批处理模拟场内对硬件仿真模型进行测试来集中访问计数事件信息。 所述硬件仿真模型的计数事件数据由仪器服务器从一个或多个仿真客户端接收。 为硬件仿真模型生成第一和第二计数器报告，其中第一和第二计数器报告是从由仪器服务器接收的计数事件数据导出的。 将第一个计数器报告与第二个计数器报告进行比较，并根据此比较，在仪表服务器内生成一个反差异报告，传达与不同模拟测试用例下的仿真模型相关的计数事件趋势。

公开(公告)号：US20100153898A1

公开(公告)日：2010-06-17

申请号：US12335766

申请日：2008-12-16

申请人： Wolfgang Roesner ,  Robert J. Shadowen ,  Derek E. Williams

发明人： Wolfgang Roesner ,  Robert J. Shadowen ,  Derek E. Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： One or more hardware description language (HDL) files describe a plurality of hierarchically arranged design entities defining a digital design to be simulated and a plurality of configuration entities not belonging to the digital design that logically control settings of a plurality of configuration latches in the digital design. The HDL file(s) are compiled to obtain a simulation executable model of the digital design and an associated configuration database. The compiling includes parsing a configuration statement that specifies an association between an instance of a configuration entity and a specified configuration latch, determining whether or not the specified configuration latch is described in the HDL file(s), and if not, creating an indication in the configuration database that the instance of the configuration latch had a specified association to a configuration latch to which it failed to bind.

摘要翻译： 一个或多个硬件描述语言（HDL）文件描述了定义要仿真的数字设计的多个分层布置的设计实体以及不属于数字设计的多个配置实体，所述多个配置实体逻辑地控制数字的多个配置锁存器的设置 设计。 编译HDL文件以获得数字设计的模拟可执行模型和相关联的配置数据库。 编译包括解析配置语句，该配置语句指定配置实体的实例与指定的配置锁存器之间的关联，确定在HDL文件中是否描述了指定的配置锁存器，以及如果不是，则创建指示 配置数据库，配置锁存器的实例与其无法绑定到的配置锁存器具有指定的关联。

公开(公告)号：US20100013005A1

公开(公告)日：2010-01-21

申请号：US12173524

申请日：2008-07-15

申请人： Wolfgang Roesner ,  Franz Hofmann

发明人： Wolfgang Roesner ,  Franz Hofmann

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7827 ,  H01L21/2255 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10876 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/66734 ,  H01L29/7813

摘要： An integrated circuit including a vertical transistor and method of manufacturing. In one embodiment a vertical transistor is formed in a pillar of a semiconductor substrate. A buried conductive line is separated from the semiconductor substrate by a first insulating layer in a first portion and is electrically coupled to a buried source/drain region of the vertical transistor through a contact structure. A second insulating layer is arranged above and adjacent to the contact structure. At least one of the first and second insulating layers includes a dopant. A doped region is formed in the semiconductor substrate at an interface to the at least one insulating layer. The doped region has a dopant concentration higher than a substrate dopant concentration.

摘要翻译： 一种包括垂直晶体管和制造方法的集成电路。 在一个实施例中，垂直晶体管形成在半导体衬底的柱中。 埋入导线通过第一部分中的第一绝缘层与半导体衬底分离，并通过接触结构电耦合到垂直晶体管的掩埋源/漏区。 第二绝缘层布置在接触结构的上方并与之相邻。 第一和第二绝缘层中的至少一个包括掺杂剂。 掺杂区域形成在半导体衬底中与至少一个绝缘层的界面处。 掺杂区域的掺杂浓度高于衬底掺杂剂浓度。