公开(公告)号：US06990530B1

公开(公告)日：2006-01-24

申请号：US09896507

申请日：2001-06-29

申请人： Gavin G. Gibson ,  Sam Gibson ,  Yuan Zhang

发明人： Gavin G. Gibson ,  Sam Gibson ,  Yuan Zhang

IPC分类号： G06F15/16 ,  G06F11/00

CPC分类号： G06F11/2221 ,  H04L69/40

摘要： Methods, systems and programs for isolating faults in a network loop is described. The link between the last device and the initiator in the network loop is tested. The loop segment between the initiator and the last device in the network loop is testesd. If a faulty link is identified in the loop segment between the initiator and the last device, then a faulty loop segment is identified and the faulty link within the faulty loop segment is isolated. For various embodiment of the present invention, divide and conquer testing or other systematic testing methods may be used to isolate the faulty link.

摘要翻译： 描述了用于隔离网络环路故障的方法，系统和程序。 测试网络环路中最后一台设备与启动器之间的链路。 网络环路中发起者和最后一个设备之间的环路段是testesd。 如果在发起方和最后一个设备之间的环路段中识别出故障链路，则识别故障环路段，并且隔离故障环路段内的故障链路。 对于本发明的各种实施例，可以使用分割和征服测试或其他系统测试方法来隔离故障链路。

公开(公告)号：US06865689B1

公开(公告)日：2005-03-08

申请号：US09896662

申请日：2001-06-29

申请人： Gavin G. Gibson ,  Sam Gibson ,  Yuan Zhang

发明人： Gavin G. Gibson ,  Sam Gibson ,  Yuan Zhang

IPC分类号： G06F11/00

CPC分类号： G06F11/263 ,  H04L43/50

摘要： Methods, systems and programs for isolating faults in a network loop are described. A single write and multiple read test is performed on the last device in a network loop to determine whether the link between the last device and the initiator is a faulty link. A multiple write test is performed on the last device to determine whether the loop segment between the initiator and the last device includes at least one faulty link. If a write error is identified, then the low level error counters of each network device are monitored. The network device with the updated error counter is identified such that the device before that network device in the network loop is selected as the first test device to be used in isolating a faulty link between the initiator and the last device.

摘要翻译： 描述了用于隔离网络环路故障的方法，系统和程序。 在网络循环中的最后一个设备上执行单次写入和多次读取测试，以确定最后一个设备和启动器之间的链路是否是故障链路。 在最后一个设备上执行多次写入测试，以确定发起者和最后一个设备之间的环路段是否包含至少一个故障链路。 如果识别出写入错误，则监视每个网络设备的低级错误计数器。 识别具有更新的错误计数器的网络设备，使得在网络环路中的网络设备之前的设备被选择为用于隔离发起者和最后一个设备之间的故障链路的第一测试设备。

公开(公告)号：US6134647A

公开(公告)日：2000-10-17

申请号：US290879

申请日：1999-04-14

申请人： John D. Acton ,  Michael D. Derbish ,  Gavin G. Gibson ,  Jack M. Hardy, Jr. ,  Hugh M. Humphreys ,  Steven P. Kent ,  Steven E. Schelong ,  Ricardo Yong ,  William B. DeRolf

发明人： John D. Acton ,  Michael D. Derbish ,  Gavin G. Gibson ,  Jack M. Hardy, Jr. ,  Hugh M. Humphreys ,  Steven P. Kent ,  Steven E. Schelong ,  Ricardo Yong ,  William B. DeRolf

IPC分类号： G06F15/173 ,  G06F15/78 ,  H04L12/42 ,  G06F15/00

CPC分类号： G06F15/17381 ,  G06F15/7864 ,  H04L12/42

摘要： A data processing system includes a plurality of nodes, a serial data bus interconnecting the nodes in series in a closed loop for passing address and data information, and at least one processing node. In one construction, this processing node has a processor, a printed circuit board, a memory partitioned into first and second sections and a local bus connecting the processor, a block sharable memory section of the memory, and the printed circuit board. The local bus is used for transferring data in parallel from the processor to a directly sharable memory section of the memory on the printed circuit board and for transferring data from the block sharable memory to the printed circuit board. The printed circuit board includes a sensor for sensing when data is transferred into the directly sharable memory, a queuing device for queuing the sensed data, a serializer for serializing the queued data, a transmitter for transmitting the serialized data onto the serial data bus to the next successive processing node, a receiver for receiving serialized data from next preceding processing node, and a deserializer for deserializing the received serialized data into parallel data.

摘要翻译： 数据处理系统包括多个节点，串行数据总线将节点串联连接在用于传递地址和数据信息的闭环中，以及至少一个处理节点。 在一个结构中，该处理节点具有处理器，印刷电路板，划分成第一和第二部分的存储器以及连接处理器，存储器的块可共享存储器部分和印刷电路板的本地总线。 本地总线用于从处理器并行传输数据到印刷电路板上存储器的直接共享存储器部分，并将数据从块可共享存储器传送到印刷电路板。 印刷电路板包括用于感测数据被传送到直接共享的存储器中的传感器，用于对感测数据进行排队的排队装置，串行化排队数据的串行器，用于将串行数据发送到串行数据总线上的发送器， 下一个连续处理节点，用于从下一个前一个处理节点接收串行化数据的接收器，以及用于反序列化所接收的串行化数据到并行数据的解串器。

公开(公告)号：US07131032B2

公开(公告)日：2006-10-31

申请号：US10389642

申请日：2003-03-13

申请人： Gavin G. Gibson ,  Todd H. McKenney ,  Christian Cadieux ,  Paula C. Kiser

发明人： Gavin G. Gibson ,  Todd H. McKenney ,  Christian Cadieux ,  Paula C. Kiser

IPC分类号： G06F11/00

CPC分类号： H04L1/22

摘要： Provided are a method, system and article of manufacture for fault determination. A duration of time is determined for receiving an event. A plurality of events are received in a time period that is at least twice the determined duration. A plurality of factors are determined corresponding to the plurality of events. At least one factor is determined from the plurality of factors, wherein the at least one factor is a cause of at least one of the plurality of events.

摘要翻译： 提供了一种用于故障确定的方法，系统和制造。 确定接收事件的持续时间。 在至少是确定的持续时间的两倍的时间段中接收多个事件。 对应于多个事件确定多个因素。 从多个因素确定至少一个因素，其中至少一个因素是多个事件中的至少一个的原因。

公开(公告)号：US06442670B2

公开(公告)日：2002-08-27

申请号：US09899371

申请日：2001-07-02

申请人： John D. Acton ,  Michael D. Derbish ,  Gavin G. Gibson ,  Jack M. Hardy, Jr. ,  Hugh M. Humphreys ,  Steven P. Kent ,  Steven E. Schelong ,  Ricardo Yong ,  William B. DeRolf

发明人： John D. Acton ,  Michael D. Derbish ,  Gavin G. Gibson ,  Jack M. Hardy, Jr. ,  Hugh M. Humphreys ,  Steven P. Kent ,  Steven E. Schelong ,  Ricardo Yong ,  William B. DeRolf

IPC分类号： G06F1500

CPC分类号： G06F15/7864 ,  G06F15/17381

摘要： A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board. The printed circuit board includes a sensor for sensing when data is transferred into the directly sharable memory, a queuing device for queuing the sense data, a serializer for serializing queued data, a transmitter for transmitting serialized data onto the serial bus to a next successive processing node, a receiver for receiving serialized data from a preceding processing node, and a deserializer for transforming received serialized data into a parallel format.

摘要翻译： 数据处理系统包括多个节点和串行数据总线，这些节点将节点串联在闭环中，用于传递地址和数据信息。 至少一个处理节点包括处理器，印刷电路板和被划分成多个部分的存储器，该存储器包括位于印刷电路板上的用于直接共享存储器的第一部分和用于阻止可共享存储器的第二部分。 本地总线连接处理器，阻止共享存储器和印刷电路板，用于将数据从处理器并行传输到印刷电路板上的直接共享存储器，并将数据从块可共享存储器传送到印刷电路板。 印刷电路板包括用于感测何时将数据传送到直接共享的存储器中的传感器，用于排列感测数据的排队装置，用于串行排队的数据的串行器，用于将串行化数据发送到串行总线上的下一个连续处理 节点，用于从前一处理节点接收串行化数据的接收器，以及用于将接收到的串行化数据变换成并行格式的解串器。

公开(公告)号：US07165192B1

公开(公告)日：2007-01-16

申请号：US10741399

申请日：2003-12-19

申请人： Christian Cadieux ,  Gavin G. Gibson

发明人： Christian Cadieux ,  Gavin G. Gibson

IPC分类号： G06F11/00

CPC分类号： H04L41/0631 ,  H04L41/0677 ,  H04L43/12

摘要： In some embodiments, a computer accessible medium comprises a plurality of instructions which, when executed, probe nodes in a network to determine if one or more nodes are experiencing any events indicative of a fault. The nodes are probed in a sequence. The instructions, when executed, in response to receiving a first alert transmitted by a first node in the network asynchronous to the probes performed according to the sequence, probe one or more neighbor nodes of the first node. In some other embodiments, the instructions, when executed, in response to receiving a first alert transmitted by a first node in the network asynchronous to the probes performed according to the sequence, interrupt probing according to the sequence to probe at least the first node.

摘要翻译： 在一些实施例中，计算机可访问介质包括多个指令，所述指令在被执行时是网络中的探测节点，以确定一个或多个节点是否经历指示故障的任何事件。 节点按顺序进行探测。 所述指令在被执行时响应于接收到由所述网络中的第一节点发送的与所述探测器所执行的所述探测异步的第一警报，探测所述第一节点的一个或多个邻居节点。 在一些其他实施例中，指令当被执行时响应于接收到由网络中的第一节点发送的与根据该序列执行的探测异步的第一警报，根据要至少探测第一节点的序列进行中断探测。

公开(公告)号：US06256722B1

公开(公告)日：2001-07-03

申请号：US09459432

申请日：1999-12-13

申请人： John D. Acton ,  Michael D. Derbish ,  Gavin G. Gibson ,  Jack M. Hardy, Jr. ,  Hugh M. Humphreys ,  Steven P. Kent ,  Steven E. Schelong ,  Ricardo Yong ,  William B. DeRolf

发明人： John D. Acton ,  Michael D. Derbish ,  Gavin G. Gibson ,  Jack M. Hardy, Jr. ,  Hugh M. Humphreys ,  Steven P. Kent ,  Steven E. Schelong ,  Ricardo Yong ,  William B. DeRolf

IPC分类号： G06F1500

CPC分类号： G06F15/17381 ,  G06F15/7864 ,  H04L12/42

摘要： A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board. The printed circuit board includes a sensor for sensing when data is transferred into the directly sharable memory, a queuing device for queuing the sense data, a serializer for serializing queued data, a transmitter for transmitting serialized data onto the serial bus to a next successive processing node, a receiver for receiving serialized data from a preceding processing node, and a deserializer for transforming received serialized data into a parallel format.

摘要翻译： 数据处理系统包括多个节点和串行数据总线，这些节点将节点串联在闭环中，用于传递地址和数据信息。 至少一个处理节点包括处理器，印刷电路板和被划分成多个部分的存储器，该存储器包括位于印刷电路板上的用于直接共享存储器的第一部分和用于阻止可共享存储器的第二部分。 本地总线连接处理器，阻止共享存储器和印刷电路板，用于将数据从处理器并行传输到印刷电路板上的直接共享存储器，并将数据从块可共享存储器传送到印刷电路板。 印刷电路板包括用于感测何时将数据传送到直接共享的存储器中的传感器，用于排列感测数据的排队装置，用于串行排队的数据的串行器，用于将串行化数据发送到串行总线上的下一个连续处理 节点，用于从前一处理节点接收串行化数据的接收器，以及用于将接收到的串行化数据变换成并行格式的解串器。

公开(公告)号：US06094532A

公开(公告)日：2000-07-25

申请号：US826805

申请日：1997-03-25

申请人： John D. Acton ,  Michael D. Derbish ,  Gavin G. Gibson ,  Jack M. Hardy, Jr. ,  Hugh M. Humphreys ,  Steven P. Kent ,  Steven E. Schelong ,  Ricardo Yong ,  William B. DeRolf

发明人： John D. Acton ,  Michael D. Derbish ,  Gavin G. Gibson ,  Jack M. Hardy, Jr. ,  Hugh M. Humphreys ,  Steven P. Kent ,  Steven E. Schelong ,  Ricardo Yong ,  William B. DeRolf

IPC分类号： G06F15/173 ,  G06F15/78 ,  H04L12/42 ,  G06F15/00

CPC分类号： G06F15/17381 ,  G06F15/7864 ,  H04L12/42

摘要： A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data information. At least one processing node includes a processor, a printed circuit board and a memory which is partitioned into a plurality of sections, including a first section for directly sharable memory located on the printed circuit board, and a second section for block sharable memory. A local bus connects the processor, block sharable memory and printed circuit board, for transferring data in parallel from the processor to the directly sharable memory on the printed circuit board, and for transferring data from the block sharable memory to the printed circuit board. The printed circuit board includes a sensor for sensing when data is transferred into the directly sharable memory, a queuing device for queuing the sense data, a serializer for serializing queued data, a transmitter for transmitting serialized data onto the serial bus to a next successive processing node, a receiver for receiving serialized data from a preceding processing node, and a deserializer for transforming received serialized data into a parallel format.

摘要翻译： 数据处理系统包括多个节点和串行数据总线，这些节点将节点串联在闭环中，用于传递地址和数据信息。 至少一个处理节点包括处理器，印刷电路板和被划分成多个部分的存储器，该存储器包括位于印刷电路板上的用于直接共享存储器的第一部分和用于阻止可共享存储器的第二部分。 本地总线连接处理器，阻止共享存储器和印刷电路板，用于将数据从处理器并行传输到印刷电路板上的直接共享存储器，并将数据从块可共享存储器传送到印刷电路板。 印刷电路板包括用于感测何时将数据传送到直接共享的存储器中的传感器，用于排列感测数据的排队装置，用于串行排队的数据的串行器，用于将串行化数据发送到串行总线上的下一个连续处理 节点，用于从前一处理节点接收串行化数据的接收器，以及用于将接收到的串行化数据变换成并行格式的解串器。