公开(公告)号：US4323862A

公开(公告)日：1982-04-06

申请号：US138064

申请日：1980-04-07

申请人： Robert Boudault ,  Gerard Pouzoullic

发明人： Robert Boudault ,  Gerard Pouzoullic

IPC分类号： H04L27/12 ,  H03C3/02 ,  H03K7/06

CPC分类号： H04L27/12

摘要： The frequency shift modulator comprises an operational amplifier connected so as to form an integrating circuit and followed by a bistable circuit having trigger hysteresis for producing a two-level voltage which is applied to one end of a first resistor whose other end is coupled to an input of the operational amplifier. Logic means are provided for applying a voltage equal or complementary to the said two-level voltage, depending upon the level of the data signal, to one end of a second resistor whose other end is joined with the said other end of the first resistor. Further logic means are provided for applying a voltage equal or complementary to the said two-level voltage, depending on whether the desired modulated signal has either the one or the other central frequency, to one end of a third resistor whose other end is joined with the joined ends of the first and second resistors. Finally, a common resistor is connected between the joined ends of the three above-mentioned resistors and the input of the operational amplifier.

摘要翻译： 频移调制器包括一个运算放大器，连接成一个积分电路，后面是一个具有触发滞后功能的双稳态电路，用于产生一个两级电压，该电平施加到第一个电阻的另一端耦合到一个输入端 的运算放大器。 提供逻辑装置，用于根据数据信号的电平将与所述两级电压相等或互补的电压施加到另一端与第一电阻器的另一端相连的第二电阻器的一端。 提供另外的逻辑装置，用于根据所需的调制信号是否具有一个或另一个中心频率，将等于或互补于所述两电平的电压施加到另一端与第二电阻器的另一端连接的第三电阻器的一端 第一和第二电阻器的接合端。 最后，在三个上述电阻器的连接端和运算放大器的输入端之间连接一个公共电阻。

公开(公告)号：US4980647A

公开(公告)日：1990-12-25

申请号：US334850

申请日：1989-04-06

申请人： Gerard Pouzoullic

发明人： Gerard Pouzoullic

IPC分类号： H04L25/02 ,  H04L12/26 ,  H04L25/06

CPC分类号： H04L1/248

摘要： An arrangement for measuring and cancelling bias distortion is designed for correcting the distortion of the binary signals which do not comprise any zero-frequency spectral components, automatically and cyclically measures said distoration (DM) by consecutive analyses of the binary data at a sampling frequency (SCK) which is a multiple of the data frequency in order to determine the sign and the quantized value of the distortion (UDC). It includes distortion cancelling means (CC) which augment the length of the binary elements selectively as a function of the sign of the distortion and proportionally to the quantized value of the said distortion and this is done until the distortion is cancelled completely.

摘要翻译： 用于测量和消除偏置失真的装置被设计用于校正不包括任何零频谱分量的二进制信号的失真，并且以采样频率（二进制数据）的二进制数据的连续分析来循环地测量所述发散（DM） SCK），其是数据频率的倍数，以便确定失真的符号和量化值（UDC）。 它包括失真消除装置（CC），其根据失真的符号有选择地增加二进制元件的长度，并且与所述失真的量化值成比例地增加二进制元件的长度，直到完全消除失真。

公开(公告)号：US5550461A

公开(公告)日：1996-08-27

申请号：US156490

申请日：1993-11-23

申请人： Gerard Pouzoullic

发明人： Gerard Pouzoullic

IPC分类号： G05F1/56 ,  G05F1/59 ,  H02J1/10 ,  G06F1/614

CPC分类号： G05F1/59 ,  H02J1/102 ,  H02J1/108

摘要： The power supply modules, together feeding a load (between the terminals 13 and 12) with the voltage V.sub.0, comprise blocking diodes D.sub.1 (or D.sub.2). A feedback loop controls the output voltage (controller 14 and comparator 15 which receives V.sub.ref1 (or V.sub.ref2)). Two output voltage terminals are used for locking, on the two electrodes of D.sub.1, the voltages V.sub.1 and V.sub.0 (or D.sub.2 with the voltage V.sub.2 and V.sub.0), and are connected to inputs of output voltage selection means (31) which are suitable to supply either the voltage kV.sub.0 (k.ltoreq.1) when D.sub.1 (or D.sub.2) is conductive, or the voltage kV.sub.1 =V.sub.ref1 (or kV.sub.2 =V.sub.ref2) when D.sub.1 (or D.sub.2) is blocked.

摘要翻译： 一起将负载（端子13和12之间）馈送到电压V0的电源模块包括阻塞二极管D1（或D2）。 反馈环路控制输出电压（控制器14和接收Vref1（或Vref2）的比较器15）。 两个输出电压端子用于锁定D1的两个电极上的电压V1和V0（或具有电压V2和V0的D2），并连接到输出电压选择装置（31）的输入端，适合供电 当D1（或D2）导通时，电压kV0（k <= 1），或当D1（或D2）被阻塞时，电压kV1 = Vref1（或kV2 = Vref2）。

公开(公告)号：US4435682A

公开(公告)日：1984-03-06

申请号：US276600

申请日：1981-06-23

申请人： Robert Boudault ,  Gerard Pouzoullic

发明人： Robert Boudault ,  Gerard Pouzoullic

IPC分类号： H03D3/06 ,  H03D3/02 ,  H03D3/20 ,  H03K9/06 ,  H04L27/14 ,  H04L27/156

CPC分类号： H03D3/20 ,  H03K9/06 ,  H04L27/1563 ,  H03D2200/0039 ,  H03D2200/0096

摘要： A frequency demodulator including an "exclusive-OR" circuit receiving two square-wave signals having a frequency corresponding to a frequency-modulated signal, and a delay circuit for delaying one of the square-wave signals before application to the "exclusive-OR" circuit, by a delay varying versus frequency in such a way that the absolute value of the phase difference between the square-wave signals varies at most from 0.degree. to 180.degree. inversely with respect to changes in frequency. The output signal of the demodulator is supplied by a low-pass filter connected to the output of the "exclusive-OR" circuit.

摘要翻译： 一种频率解调器，包括接收具有与频率调制信号相对应的频率的两个方波信号的“异或”电路，以及延迟电路，用于在施加到“异或”之前将方波信号之一延迟 电路通过延迟变化对频率的方式使得方波信号之间的相位差的绝对值相对于频率变化相反地变化到0°至180°。 解调器的输出信号由连接到“异或”电路的输出的低通滤波器提供。