公开(公告)号：US20140025892A1

公开(公告)日：2014-01-23

申请号：US13551335

申请日：2012-07-17

Applicant: Gerard R. Williams III

Inventor： Gerard R. Williams III

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/6028

Abstract: Methods, apparatuses, and processors for reducing memory latency in the presence of barriers. When a barrier operation is executed, subsequent memory access operations are delayed until the barrier operation retires. While the memory access operation is delayed, the memory access operation is converted into a prefetch request and sent to the L2 cache. Then, data corresponding to the prefetch request is retrieved and stored in the L1 data cache. When the memory access operation wakes up, the data for the operation will already be stored in the L1 data cache, reducing the memory latency of the operation.

Abstract translation: 用于在存在障碍的情况下减少内存延迟的方法，设备和处理器。 当执行屏障操作时，后续存储器访问操作被延迟直到屏障操作退出。 当存储器访问操作被延迟时，存储器访问操作被转换为预取请求并被发送到L2缓存。 然后，检索与预取请求对应的数据并存储在L1数据高速缓存中。 当内存访问操作唤醒时，操作数据已经存储在L1数据缓存中，从而减少了操作的内存延迟。