公开(公告)号：US20100278277A1

公开(公告)日：2010-11-04

申请号：US12547035

申请日：2009-08-25

申请人： Gi Yoon PARK ,  Ok-Sun PARK ,  Dae Soon CHO ,  Hyeong Jun PARK

发明人： Gi Yoon PARK ,  Ok-Sun PARK ,  Dae Soon CHO ,  Hyeong Jun PARK

IPC分类号： H04L1/02

CPC分类号： H04L27/2647 ,  H04L1/0631 ,  H04L1/0643 ,  H04L1/0668

摘要： Provided is a decoding apparatus and method using orthogonal space-time block codes (OSTBCs) robust against timing errors. The decoding apparatus may include: a cyclic prefix removal unit to receive a signal, and to remove a cyclic prefix in the signal; an inverse discrete Fourier transform (IDFT) unit to apply an IDFT to the signal with the removed cyclic prefix; a guard band removal unit to remove a guard band in the inverse discrete Fourier transformed signal, and to generate a complex matrix; a channel estimation unit to transmit a carrier corresponding to the complex matrix and channel status information associated with transmit and receive antennas; and a decoder to calculate a channel status vector with respect to a complex symbol included in the complex matrix, using the channel status information, and to calculate an inner product between the channel status vector and the complex matrix, to restore the complex symbol.

摘要翻译： 提供了一种使用对定时误差鲁棒的正交空时块码（OSTBC）的解码装置和方法。 解码装置可以包括：循环前缀去除单元，用于接收信号，并去除信号中的循环前缀; 反向离散付里叶变换（IDFT）单元，用于将IDFT应用于具有去除的循环前缀的信号; 保护带去除单元，用于去除离散付里叶逆变换信号的保护带，并产生复数矩阵; 信道估计单元，用于发送对应于复数矩阵的载波和与发射和接收天线相关联的信道状态信息; 以及解码器，使用信道状态信息来计算相对于复数矩阵中包括的复数符号的信道状态向量，并计算信道状态向量和复矩阵之间的内积，以恢复复数符号。

公开(公告)号：US20100158053A1

公开(公告)日：2010-06-24

申请号：US12544645

申请日：2009-08-20

申请人： Eun Tae KIM ,  Dae Soon CHO ,  Hee Sang CHUNG ,  Hyeong Jun PARK

发明人： Eun Tae KIM ,  Dae Soon CHO ,  Hee Sang CHUNG ,  Hyeong Jun PARK

IPC分类号： H04J3/04

CPC分类号： H04L1/0052 ,  H04L1/0067 ,  H04L1/0071

摘要： Provided are a method and apparatus for derate matching a rate-matched data. The received data is deinterleaved and derate matched at a time, without using input buffers or constructing input buffers in parallel. Thus, a total process time necessary for the deinterleaving process and the derate matching process is reduced, and the use of memories such as the input buffers is minimized.

摘要翻译： 提供了一种降低匹配速率匹配数据的方法和装置。 接收到的数据一次被解交错和降额匹配，而不使用输入缓冲器或并行构建输入缓冲器。 因此，减少解交织处理和降额匹配处理所需的总处理时间，并且使诸如输入缓冲器的存储器的使用最小化。

公开(公告)号：US20120069915A1

公开(公告)日：2012-03-22

申请号：US13020143

申请日：2011-02-03

申请人： Dae Soon CHO ,  EunTae KIM ,  Hee Sang CHUNG ,  JungSook BAE ,  Daeho KIM

发明人： Dae Soon CHO ,  EunTae KIM ,  Hee Sang CHUNG ,  JungSook BAE ,  Daeho KIM

IPC分类号： H04L27/00

CPC分类号： H04L1/0067 ,  H04L1/0071

摘要： Provided is a rate matching apparatus. The rate matching apparatus includes interleavers, dummy bit removers, a bit collector, a memory and a selector. The interleavers interleave code blocks, respectively. The dummy bit removers remove dummy bits of the interleaved code blocks, respectively. The bit collector collects code blocks with the dummy bits removed by bit units, and divides a collected data bit stream into systematic data and parity data. The memory stores the systematic data and the parity data in parallel. The selector outputs in parallel a plurality of data bits which are selected from the systematic data and parity data of the memory.

摘要翻译： 提供了一种速率匹配装置。 速率匹配装置包括交织器，伪位去除器，位收集器，存储器和选择器。 交织器分别交替代码块。 虚拟位去除器分别去除交织代码块的虚拟位。 位收集器采集通过位单元去除虚拟位的代码块，并将收集的数据位流分成系统数据和奇偶校验数据。 存储器并行地存储系统数据和奇偶校验数据。 选择器并行输出从存储器的系统数据和奇偶校验数据中选择的多个数据位。

公开(公告)号：US20120066283A1

公开(公告)日：2012-03-15

申请号：US13222108

申请日：2011-08-31

申请人： Dae Soon CHO ,  Daeho KIM

发明人： Dae Soon CHO ,  Daeho KIM

IPC分类号： G06F7/52

CPC分类号： G06F7/535 ,  G06F2207/5354

摘要： Provided are a divider having a small area and an improved operation speed and a method of operating the same. The divider includes a memory, a controller, and a multiplier. The memory is configured to store table values included in a predetermined range. The controller is configured to receive a divisor, generate an address expressed in a plurality of bits according to the bits except the most significant bit of the divisor, and receive the table value corresponding to the address from the memory. The multiplier is configured to receive a dividend and calculate an initial value by multiplying the dividend and the table value corresponding to the address. Herein, the controller determines an exponent of the divisor and right-shifts the initial value by the exponent of the divisor.

摘要翻译： 提供具有小面积和改进的操作速度的分隔器及其操作方法。 分频器包括一个存储器，一个控制器和一个乘法器。 存储器被配置为存储包括在预定范围内的表值。 控制器被配置为接收除数，根据除数除数最高有效位之外的比特生成以多个比特表示的地址，并且从存储器接收对应于地址的表值。 乘数被配置为通过乘以与该地址相对应的被除数和表值来计算初始值。 这里，控制器确定除数的指数，并按照除数的指数对初始值进行右移。