公开(公告)号：US20240267042A1

公开(公告)日：2024-08-08

申请号：US18158572

申请日：2023-01-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Thomas G. McKay ,  Gail B. Katzman

IPC: H03K17/16 ,  H03K3/012

CPC classification number: H03K17/161 ,  H03K3/012

Abstract: A disclosed structure (e.g., a switch circuit) includes multiple transistors (e.g., on triple wells) connected in series between a first and second nodes. Each transistor can include a primary gate (e.g., a front gate) for controlling the ON/OFF state of the transistor and a secondary gate (e.g., a back gate) for adjusting the VT of the transistor. The switch circuit further includes multiple capacitors (e.g., APMOM capacitors on triple wells), each connected to the second node and to the secondary gate of a corresponding one of the transistors. In advanced semiconductor-on-insulator processing technology platforms, each secondary gate includes a well region within a semiconductor substrate and a corresponding section of an insulator layer, which is on the semiconductor substrate and adjacent to an active device region for the transistor. The capacitors are preselected during design and different capacitances for limiting parasitic secondary gate-to-substrate coupling. Also disclosed are associated methods.