公开(公告)号：US20240429128A1

公开(公告)日：2024-12-26

申请号：US18340220

申请日：2023-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam Dutta ,  Satyasuresh VVss Choppalli ,  Rui Tze Toh

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H01L29/78

Abstract: Disclosed structures and methods include a top chip flipped relative to a bottom chip and bonded thereto. On the top chip, dielectric material layers separate a transistor from the bottom chip. The transistor includes source and drain regions; a body region on a channel region between the source and drain regions; and a gate structure adjacent to and between the channel region and the dielectric material layers. Alternatively, the transistor includes: a source region between drain regions; a body region on a channel region between the source region and each drain region; and gate structures adjacent to and between the channel regions and the dielectric material layers. The first chip also includes an insulator layer on the transistor opposite the dielectric material layers, a trench in the insulator layer extending to the source and body regions, and a local interconnect at the bottom of the trench.