公开(公告)号：US08682815B1

公开(公告)日：2014-03-25

申请号：US13847748

申请日：2013-03-20

Applicant: Google Inc.

Inventor： Dennis Charles Abts ,  Daniel Gibson

IPC: G06F15/18

CPC classification number: G06F12/0813 ,  G06F15/17312 ,  G06F17/5072 ,  G06F17/5077

Abstract: The location of the memory controllers within the on-chip fabric of multiprocessor architectures plays a central role in latency bandwidth characteristics of the processor-to-memory traffic. Intelligent placement substantially reduces the maximum channel load depending on the specific memory controller configuration selected. A variety of simulation techniques are used along and in combination to determine optimal memory controller arrangements. Diamond-type and diagonal X-type memory controller configurations that spread network traffic across all rows and columns in a multiprocessor array substantially improve over other arrangements. Such placements reduce interconnect latency by an average of 10% for real workloads, and the small number of memory controllers relative to the number of on-chip cores opens up a rich design space to optimize latency and bandwidth characteristics of the on-chip network.

Abstract translation: 多处理器架构的片上架构内的存储器控​​制器的位置在处理器到存储器流量的延迟带宽特性中起着核心作用。 根据所选择的特定内存控制器配置，智能放置可显着降低最大通道负载。 各种模拟技术沿着并结合使用以确定最佳的存储器控​​制器布置。 在多处理器阵列中跨所有行和列传播网络流量的钻石型和对角X型存储器控制器配置大大改进了其他布置。 这样的布局将实际工作负载的互连延迟平均降低了10％，而相对于片上内核数量的少量内存控制器开辟了丰富的设计空间，以优化片上网络的延迟和带宽特性。

公开(公告)号：US09158688B1

公开(公告)日：2015-10-13

申请号：US14182579

申请日：2014-02-18

Applicant: Google Inc.

Inventor： Dennis C. Abts ,  Daniel Gibson

IPC: G06F15/18 ,  G06F12/08 ,  G06F17/50

CPC classification number: G06F12/0813 ,  G06F15/17312 ,  G06F17/5072 ,  G06F17/5077

Abstract: The location of the memory controllers within the on-chip fabric of multiprocessor architectures plays a central role in latency bandwidth characteristics of the processor-to-memory traffic. Intelligent placement substantially reduces the maximum channel load depending on the specific memory controller configuration selected. A variety of simulation techniques are used along and in combination to determine optimal memory controller arrangements. Diamond-type and diagonal X-type memory controller configurations that spread network traffic across all rows and columns in a multiprocessor array substantially improve over other arrangements. Such placements reduce interconnect latency by an average of 10% for real workloads, and the small number of memory controllers relative to the number of on-chip cores opens up a rich design space to optimize latency and bandwidth characteristics of the on-chip network.

Abstract translation: 多处理器架构的片上架构内的存储器控​​制器的位置在处理器到存储器流量的延迟带宽特性中起着核心作用。 根据所选择的特定内存控制器配置，智能放置可显着降低最大通道负载。 各种模拟技术沿着并结合使用以确定最佳的存储器控​​制器布置。 在多处理器阵列中跨所有行和列传播网络流量的钻石型和对角X型存储器控制器配置大大改进了其他布置。 这样的布局将实际工作负载的互连延迟平均降低了10％，而相对于片上内核数量的少量内存控制器开辟了丰富的设计空间，以优化片上网络的延迟和带宽特性。