公开(公告)号：US20230161592A1

公开(公告)日：2023-05-25

申请号：US17972681

申请日：2022-10-25

Applicant: Google LLC

Inventor： Rahul Nagarajan ,  Christopher Leary ,  Thejasvi Magudilu Vijayaraj ,  Thomas James Norrie

IPC: G06F9/38

CPC classification number: G06F9/3802 ,  G06F9/3887

Abstract: Aspects of the disclosure are directed to methods, systems, and apparatuses using an instruction prefetch pipeline architecture that provides good performance without the complexity of a full cache coherent solution deployed in conventional CPUs. The architecture can include components which can be used to construct an instruction prefetch pipeline, including instruction memory (TiMem), instruction buffer (iBuf), a prefetch unit, and an instruction router.

公开(公告)号：US20230153116A1

公开(公告)日：2023-05-18

申请号：US17981617

申请日：2022-11-07

Applicant: Google LLC

Inventor： Rahul Nagarajan ,  Suvinay Subramanian ,  Arpith Chacko Jacob ,  Christopher Leary ,  Thomas James Norrie ,  Thejasvi Magudilu Vijayaraj ,  Hema Hariharan

IPC: G06F9/38 ,  G06F9/30 ,  G06N3/02

CPC classification number: G06F9/3895 ,  G06F9/3887 ,  G06F9/30036 ,  G06N3/02

Abstract: Aspects of the disclosure provide for an accelerator capable of accelerating data dependent, irregular, and/or memory-bound operations. An accelerator as described herein includes a programmable engine for efficiently executing computations on-chip that are dynamic, irregular, and/or memory-bound, in conjunction with a co-processor configured to accelerate operations that are predictable in computational load and behavior on the co-processor during design and fabrication.

公开(公告)号：US20240211264A1

公开(公告)日：2024-06-27

申请号：US18595866

申请日：2024-03-05

Applicant: Google LLC

Inventor： Rahul Nagarajan ,  Christopher Leary ,  Thejasvi Magudilu Vijayaraj ,  Thomas James Norrie

IPC: G06F9/38

CPC classification number: G06F9/3802 ,  G06F9/3887

Abstract: Aspects of the disclosure are directed to methods, systems, and apparatuses using an instruction prefetch pipeline architecture that provides good performance without the complexity of a full cache coherent solution deployed in conventional CPUs. The architecture can include components which can be used to construct an instruction prefetch pipeline, including instruction memory (TiMem), instruction buffer (iBuf), a prefetch unit, and an instruction router.

公开(公告)号：US11972263B2

公开(公告)日：2024-04-30

申请号：US17972681

申请日：2022-10-25

Applicant: Google LLC

Inventor： Rahul Nagarajan ,  Christopher Leary ,  Thejasvi Magudilu Vijayaraj ,  Thomas James Norrie

IPC: G06F9/38

CPC classification number: G06F9/3802 ,  G06F9/3887

Abstract: Aspects of the disclosure are directed to methods, systems, and apparatuses using an instruction prefetch pipeline architecture that provides good performance without the complexity of a full cache coherent solution deployed in conventional CPUs. The architecture can include components which can be used to construct an instruction prefetch pipeline, including instruction memory (TiMem), instruction buffer (iBuf), a prefetch unit, and an instruction router.