公开(公告)号：US20220300421A1

公开(公告)日：2022-09-22

申请号：US17425918

申请日：2020-08-19

Applicant: Google LLC

Inventor： Suyog Gupta ,  Ravi Narayanaswami ,  Uday Kumar Dasari ,  Ali Iranli ,  Pavan Thirunagari ,  Vinu Vijay Kumar ,  Sunitha R. Kosireddy

IPC: G06F12/0802 ,  G06F3/06

Abstract: Components on an IC chip may operate faster or provide higher performance relative to power consumption if allowed access to sufficient memory resources. If every component is provided its own memory, however, the chip becomes expensive. In described implementations, memory is shared between two or more components. For example, a processing component can include computational circuitry and a memory coupled thereto. A multi-component cache controller is coupled to the memory. Logic circuitry is coupled to the cache controller and the memory. The logic circuitry selectively separates the memory into multiple memory partitions. A first memory partition can be allocated to the computational circuitry and provide storage to the computational circuitry. A second memory partition can be allocated to the cache controller and provide storage to multiple components. The relative capacities of the memory partitions are adjustable to accommodate fluctuating demands without dedicating individual memories to the components.

公开(公告)号：US12013780B2

公开(公告)日：2024-06-18

申请号：US17425918

申请日：2020-08-19

Applicant: Google LLC

Inventor： Suyog Gupta ,  Ravi Narayanaswami ,  Uday Kumar Dasari ,  Ali Iranli ,  Pavan Thirunagari ,  Vinu Vijay Kumar ,  Sunitha R. Kosireddy

IPC: G06F12/0802 ,  G06F3/06

CPC classification number: G06F12/0802 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0644 ,  G06F3/0679 ,  G06F2212/60

Abstract: Components on an IC chip may operate faster or provide higher performance relative to power consumption if allowed access to sufficient memory resources. If every component is provided its own memory, however, the chip becomes expensive. In described implementations, memory is shared between two or more components. For example, a processing component can include computational circuitry and a memory coupled thereto. A multi-component cache controller is coupled to the memory. Logic circuitry is coupled to the cache controller and the memory. The logic circuitry selectively separates the memory into multiple memory partitions. A first memory partition can be allocated to the computational circuitry and provide storage to the computational circuitry. A second memory partition can be allocated to the cache controller and provide storage to multiple components. The relative capacities of the memory partitions are adjustable to accommodate fluctuating demands without dedicating individual memories to the components.