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公开(公告)号：US07784014B1
公开(公告)日：2010-08-24
申请号：US11799897
申请日：2007-05-03
申请人： Gordon J. Brebner , Christopher E. Neely , Philip B. James-Roxby , Eric R. Keller , Chidamber R. Kulkarni , Michael A. Baxter , Henry E. Styles , Graham F. Schelle
发明人： Gordon J. Brebner , Christopher E. Neely , Philip B. James-Roxby , Eric R. Keller , Chidamber R. Kulkarni , Michael A. Baxter , Henry E. Styles , Graham F. Schelle
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method is provided for generating a hardware description language (HDL) specification of a network packet processor from a textual language specification of the processing of network packets by the processor. The processor includes a look-ahead stage, an operation stage, an insert/remove stage, and an interleave stage. The textual language specification identifies the ports of the processor. The textual language specification includes formats for the type or types of the incoming and outgoing network packets. Each format includes the fields of the type of network packet. The textual language specification includes a procedure for each input port and for each type of incoming network packet received at the input port. Each procedure includes one or more actions for modifying the fields of a type of network packet as a function of state data and/or the fields of the type of network packet.
摘要翻译： 提供了一种从处理器对网络分组的处理的文本语言规范生成网络分组处理器的硬件描述语言（HDL）规范的方法。 处理器包括前视级，操作级，插入/移除级和交错级。 文本语言规范识别处理器的端口。 文本语言规范包括进出网络数据包的类型或类型的格式。 每个格式包括网络包类型的字段。 文本语言规范包括每个输入端口和在输入端口接收的每种类型的传入网络分组的过程。 每个过程包括用于根据状态数据和/或网络分组类型的字段修改网络分组类型的字段的一个或多个动作。
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2.发明授权Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip 有权专用于可编程存储器架构和芯片上互连网络的方法和装置公开(公告)号：US07185309B1
公开(公告)日：2007-02-27
申请号：US10769591
申请日：2004-01-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory system. A logical description of the memory system is generated in response to the specification data. The logical description defines a memory component and a memory-interconnection component. A physical description of the memory system is generated in response to the logical description. The physical description includes memory circuitry associated with the integrated circuit defined by the memory component. The memory circuitry includes an interconnection topology defined by the memory interconnection component.
摘要翻译： 描述了用于实现使用集成电路的消息处理系统的可编程架构。 在一个示例中，接收包括存储器系统的属性的规范数据。 响应于规范数据生成存储器系统的逻辑描述。 逻辑描述定义了存储器组件和存储器互连组件。 响应于逻辑描述生成存储器系统的物理描述。 物理描述包括与由存储器组件定义的集成电路相关联的存储器电路。 存储器电路包括由存储器互连部件定义的互连拓扑。
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公开(公告)号：US08065130B1
公开(公告)日：2011-11-22
申请号：US12465247
申请日：2009-05-13
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , H04L45/60
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of an integrated circuit is configured to have a plurality of thread circuits and a memory. Messages are received to the integrated circuit for storage in the memory. The memory is accessed with the plurality of threads to concurrently process a plurality of the messages.
摘要翻译： 描述了用于实现使用集成电路的消息处理系统的可编程架构。 在一个示例中，集成电路的可配置逻辑被配置为具有多个线程电路和存储器。 消息被接收到集成电路以存储在存储器中。 利用多个线程来访问存储器以同时处理多个消息。
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公开(公告)号：US07552042B1
公开(公告)日：2009-06-23
申请号：US10769592
申请日：2004-01-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , H04L45/60
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of an integrated circuit is configured to have a plurality of thread circuits and a memory. Messages are received to the integrated circuit for storage in the memory. The memory is accessed with the plurality of threads to concurrently process a plurality of the messages.
摘要翻译： 描述了用于实现使用集成电路的消息处理系统的可编程架构。 在一个示例中，集成电路的可配置逻辑被配置为具有多个线程电路和存储器。 消息被接收到集成电路以存储在存储器中。 利用多个线程来访问存储器以同时处理多个消息。
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5.发明授权公开(公告)号：US07770179B1
公开(公告)日：2010-08-03
申请号：US10769330
申请日：2004-01-30
CPC分类号： G06F17/5054
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, configurable logic of the integrated circuit is configured to have a plurality of thread circuits and an interconnection topology amongst the plurality of thread circuits. Messages are concurrently processed using the plurality of thread circuits. Operation of at least one thread circuit of the plurality of thread circuits is controlled in accordance with control data received via the interconnection topology from at least one other thread circuit of the plurality of thread circuits.
摘要翻译： 描述了用于实现使用集成电路的消息处理系统的可编程架构。 在一个示例中，集成电路的可配置逻辑被配置为在多个线程电路之间具有多个线程电路和互连拓扑。 使用多个线程电路同时处理消息。 根据从多个线程电路的至少一个其它线程电路经由互连拓扑接收的控制数据来控制多个线程电路中的至少一个线程电路的操作。
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6.发明授权Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip 有权专用于可编程存储器架构和芯片上互连网络的方法和装置公开(公告)号：US07574680B1
公开(公告)日：2009-08-11
申请号：US11699097
申请日：2007-01-29
IPC分类号： G06F17/50
CPC分类号： G06F17/5027
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, specification data is received that includes attributes of the memory system. A logical description of the memory system is generated in response to the specification data. The logical description defines a memory component and a memory-interconnection component. A physical description of the memory system is generated in response to the logical description. The physical description includes memory circuitry associated with the integrated circuit defined by the memory component. The memory circuitry includes an interconnection topology defined by the memory interconnection component.
摘要翻译： 描述了用于实现使用集成电路的消息处理系统的可编程架构。 在一个示例中，接收包括存储器系统的属性的规范数据。 响应于规范数据生成存储器系统的逻辑描述。 逻辑描述定义了存储器组件和存储器互连组件。 响应于逻辑描述生成存储器系统的物理描述。 物理描述包括与由存储器组件定义的集成电路相关联的存储器电路。 存储器电路包括由存储器互连部件定义的互连拓扑。
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7.发明授权Method and apparatus for a programmable interface of a soft platform on a programmable logic device 有权用于可编程逻辑器件上的软平台的可编程接口的方法和装置公开(公告)号：US07228520B1
公开(公告)日：2007-06-05
申请号：US10769331
申请日：2004-01-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Programmable architecture for implementing a message processing system using an integrated circuit is described. In an example, first attributes are defined for a plurality of threads within the integrated circuit. Second attributes are defined for a memory associated with the integrated circuit. Third attributes are defined for an interconnection topology associated with at least one of the memory and the plurality of threads. Fourth attributes are defined for an interface to at least one of the memory and the plurality of threads.
摘要翻译： 描述了用于实现使用集成电路的消息处理系统的可编程架构。 在一个示例中，为集成电路内的多个线程定义第一属性。 为与集成电路相关联的存储器定义第二属性。 为与存储器和多个线程中的至少一个相关联的互连拓扑定义第三属性。 为与至少一个存储器和多个线程的接口定义第四属性。
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公开(公告)号：US07792117B1
公开(公告)日：2010-09-07
申请号：US11799966
申请日：2007-05-03
IPC分类号： H04L12/28
CPC分类号： H04L12/4633 , H04L49/901
摘要： A method is provided for simulating a processor of network packets. A specification is input for the processor. The specification includes actions specifying a modification of the network packets by the processor. Each action includes a guard condition that enables and disables the action. First and second values of certain fields are determined for each action. The guard condition enables and disables the action respectively for the first and second values of the fields. The network packets are generated. For each field included in the guard conditions, a value of the field is selected for each generated network packet from the values of the field within the first and second values for the actions. The specification of the processor is translated into a simulator of the processor. The modification of the network packets is simulated in the simulator. A result of the modification is displayed on a user interface.
摘要翻译： 提供了一种用于模拟网络分组的处理器的方法。 为处理器输入规格。 该规范包括指定处理器对网络分组的修改的动作。 每个动作包括启用和禁用操作的保护条件。 确定每个动作的某些字段的第一个和第二个值。 保护条件分别为字段的第一个和第二个值启用和禁用该操作。 生成网络数据包。 对于包括在保护条件中的每个字段，从动作的第一和第二值内的字段的值为每个生成的网络包选择字段的值。 处理器的规格被转换成处理器的模拟器。 在模拟器中模拟网络数据包的修改。 修改的结果显示在用户界面上。
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9.发明授权Circuit for modification of a network packet by insertion or removal of a data segment 有权通过插入或删除数据段来修改网络包的电路公开(公告)号：US07788402B1
公开(公告)日：2010-08-31
申请号：US11799898
申请日：2007-05-03
CPC分类号： H04L69/08
摘要： A state machine circuit converts a first network packet into a second network packet according to modification actions from a textual language specification. Each modification action is either an insertion action inserting a data segment or a removal action removing a data segment. Each state corresponds to a pairing of a first data word from the first packet and a second data word from the second packet. Each state selects the data units of the second data word from the data segment of each insertion action and the data units of both the first and a prior data word. Each state specifies one or more next states including the state corresponding to the pairing of either the first or a next data word after the first data word in the first sequence and either the second or a next data word after the second data word in the second sequence.
摘要翻译： 状态机电路根据来自文本语言规范的修改动作将第一网络分组转换成第二网络分组。 每个修改操作是插入操作插入数据段或删除操作删除数据段。 每个状态对应于来自第一分组的第一数据字和来自第二分组的第二数据字的配对。 每个状态从每个插入动作的数据段和第一和先前数据字的数据单元中选择第二数据字的数据单元。 每个状态指定一个或多个下一状态，包括与第一序列中的第一数据字之后的第一或下一个数据字的配对相对应的状态，以及在第二序列中的第二数据字之后的第二或下一数据字 序列。
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10.发明授权Generation of executable threads having source code specifications that describe network packets 有权生成具有描述网络数据包的源代码规范的可执行线程公开(公告)号：US08032874B1
公开(公告)日：2011-10-04
申请号：US11336163
申请日：2006-01-20
CPC分类号： G06F8/4434
摘要： From source code specification of each of a plurality of threads, those variables of a data structure referenced by the thread are determined. For each thread, a respective adaptation of the source code specification of the data structure is generated. Each adaptation includes only variables of the data structure that are referenced in the respective thread. The source code specifications of the threads are compiled into respective object code segments using the respective adaptations of the data structures. Each object code segment requires memory space for the data structure for only those variables included in the respective adaptation. The source code specification of the data structure describes a network packet, and the respective object code segments are configured to operate on the respective portions of the network packet stored in separate memories while executing on respective processors.
摘要翻译： 根据多个线程中的每一个的源代码规范，确定线程引用的数据结构的那些变量。 对于每个线程，生成数据结构的源代码规范的各自的适配。 每个自适应仅包括在相应线程中引用的数据结构的变量。 使用数据结构的相应修改，将线程的源代码规范编译成各自的对象代码段。 每个目标代码段仅需要用于数据结构的存储器空间，用于仅包括在各自适配中的那些变量。 数据结构的源代码规范描述了网络分组，并且相应的目标代码段被配置为在各个处理器上执行时在存储在单独存储器中的网络分组的各个部分上进行操作。
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