Estimating system performance using an integrated circuit
    1.
    发明授权
    Estimating system performance using an integrated circuit 有权
    使用集成电路估算系统性能

    公开(公告)号:US09081925B1

    公开(公告)日:2015-07-14

    申请号:US13398790

    申请日:2012-02-16

    IPC分类号: G06F9/455 G06F17/50

    摘要: A method of estimating performance of a design can include selecting a segment of the design for hardware emulation within an emulation system implemented within an integrated circuit. The emulation system can include a generic accelerator coupled to a processor of the integrated circuit. The method further can include modifying the design, using a processor of a host system, to invoke the generic accelerator in lieu of executing the selected segment within the processor of the emulation system during emulation.

    摘要翻译: 估计设计性能的方法可以包括在集成电路内实现的仿真系统内选择用于硬件仿真的设计的一部分。 仿真系统可以包括耦合到集成电路的处理器的通用加速器。 该方法还可以包括使用主机系统的处理器来修改设计来代替在仿真期间在仿真系统的处理器内执行所选择的段的通用加速器。

    Circuit for modification of a network packet by insertion or removal of a data segment
    2.
    发明授权
    Circuit for modification of a network packet by insertion or removal of a data segment 有权
    通过插入或删除数据段来修改网络包的电路

    公开(公告)号:US07788402B1

    公开(公告)日:2010-08-31

    申请号:US11799898

    申请日:2007-05-03

    CPC分类号: H04L69/08

    摘要: A state machine circuit converts a first network packet into a second network packet according to modification actions from a textual language specification. Each modification action is either an insertion action inserting a data segment or a removal action removing a data segment. Each state corresponds to a pairing of a first data word from the first packet and a second data word from the second packet. Each state selects the data units of the second data word from the data segment of each insertion action and the data units of both the first and a prior data word. Each state specifies one or more next states including the state corresponding to the pairing of either the first or a next data word after the first data word in the first sequence and either the second or a next data word after the second data word in the second sequence.

    摘要翻译: 状态机电路根据来自文本语言规范的修改动作将第一网络分组转换成第二网络分组。 每个修改操作是插入操作插入数据段或删除操作删除数据段。 每个状态对应于来自第一分组的第一数据字和来自第二分组的第二数据字的配对。 每个状态从每个插入动作的数据段和第一和先前数据字的数据单元中选择第二数据字的数据单元。 每个状态指定一个或多个下一状态,包括与第一序列中的第一数据字之后的第一或下一个数据字的配对相对应的状态,以及在第二序列中的第二数据字之后的第二或下一数据字 序列。

    Generation of a specification of a network packet processor
    4.
    发明授权
    Generation of a specification of a network packet processor 有权
    生成网络包处理器的规范

    公开(公告)号:US07784014B1

    公开(公告)日:2010-08-24

    申请号:US11799897

    申请日:2007-05-03

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5045

    摘要: A method is provided for generating a hardware description language (HDL) specification of a network packet processor from a textual language specification of the processing of network packets by the processor. The processor includes a look-ahead stage, an operation stage, an insert/remove stage, and an interleave stage. The textual language specification identifies the ports of the processor. The textual language specification includes formats for the type or types of the incoming and outgoing network packets. Each format includes the fields of the type of network packet. The textual language specification includes a procedure for each input port and for each type of incoming network packet received at the input port. Each procedure includes one or more actions for modifying the fields of a type of network packet as a function of state data and/or the fields of the type of network packet.

    摘要翻译: 提供了一种从处理器对网络分组的处理的文本语言规范生成网络分组处理器的硬件描述语言(HDL)规范的方法。 处理器包括前视级,操作级,插入/移除级和交错级。 文本语言规范识别处理器的端口。 文本语言规范包括进出网络数据包的类型或类型的格式。 每个格式包括网络包类型的字段。 文本语言规范包括每个输入端口和在输入端口接收的每种类型的传入网络分组的过程。 每个过程包括用于根据状态数据和/或网络分组类型的字段修改网络分组类型的字段的一个或多个动作。

    Method for simulating a processor of network packets
    5.
    发明授权
    Method for simulating a processor of network packets 有权
    用于模拟网络数据包处理器的方法

    公开(公告)号:US07792117B1

    公开(公告)日:2010-09-07

    申请号:US11799966

    申请日:2007-05-03

    IPC分类号: H04L12/28

    CPC分类号: H04L12/4633 H04L49/901

    摘要: A method is provided for simulating a processor of network packets. A specification is input for the processor. The specification includes actions specifying a modification of the network packets by the processor. Each action includes a guard condition that enables and disables the action. First and second values of certain fields are determined for each action. The guard condition enables and disables the action respectively for the first and second values of the fields. The network packets are generated. For each field included in the guard conditions, a value of the field is selected for each generated network packet from the values of the field within the first and second values for the actions. The specification of the processor is translated into a simulator of the processor. The modification of the network packets is simulated in the simulator. A result of the modification is displayed on a user interface.

    摘要翻译: 提供了一种用于模拟网络分组的处理器的方法。 为处理器输入规格。 该规范包括指定处理器对网络分组的修改的动作。 每个动作包括启用和禁用操作的保护条件。 确定每个动作的某些字段的第一个和第二个值。 保护条件分别为字段的第一个和第二个值启用和禁用该操作。 生成网络数据包。 对于包括在保护条件中的每个字段,从动作的第一和第二值内的字段的值为每个生成的网络包选择字段的值。 处理器的规格被转换成处理器的模拟器。 在模拟器中模拟网络数据包的修改。 修改的结果显示在用户界面上。