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公开(公告)号：US07471831B2
公开(公告)日：2008-12-30
申请号：US10759808
申请日：2004-01-16
IPC分类号： G06K9/46
CPC分类号： G01N15/1463 , G01N2015/1497 , H04N5/335 , H04N5/347
摘要： The present invention relates to a system and method for performing rapid and programmable analysis of data. The present invention relates to a reconfigurable detector comprising at least one array of a plurality of pixels, where each of the plurality of pixels can be selected to receive and read-out an input. The pixel array is divided into at least one pixel group for conducting a common predefined analysis. Each of the pixels has a programmable circuitry programmed with a dynamically configurable user-defined function to modify the input. The present detector also comprises a summing circuit designed to sum the modified input.
摘要翻译： 本发明涉及用于执行数据的快速和可编程分析的系统和方法。 本发明涉及可重构检测器，其包括多个像素的至少一个阵列，其中可以选择多个像素中的每一个来接收和读出输入。 像素阵列被划分为用于进行公共预定义分析的至少一个像素组。 每个像素具有可编程的电路，其具有可动态配置的用户定义的功能，以修改输入。 本检测器还包括设计用于对修改的输入求和的求和电路。
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公开(公告)号：US07019345B2
公开(公告)日：2006-03-28
申请号：US10008568
申请日：2001-11-16
申请人： Bedabrata Pain , Thomas J. Cunningham , Bruce Hancock , Suresh Seshadri , Monico Ortiz , Guang Yang
发明人： Bedabrata Pain , Thomas J. Cunningham , Bruce Hancock , Suresh Seshadri , Monico Ortiz , Guang Yang
IPC分类号： H01L31/062 , H01L31/113
摘要： The present invention provides a CMOS imager with a reset scheme, by which a CMOS imager generates a sub-kTC noise so that read noise does not depend on the sense node capacitance. By using a column feedback circuit, reset noise can be suppressed to a negligible amount so that photogate APS or CCD-like circuits can achieve noise performance to very efficient value. This scheme allows increasing sense node capacitance without increasing the noise and also achieves a large full-well value without sacrificing read noise performance. The feedback circuit in one of the embodiment of the present invention is located at the column side of the circuit. This design provides a minimal change to the pixel. As a result quantum efficiency or pixel size is not compromised. The present invention allows a CMOS imager to capture scene with high intra-scene contracts under low illumination with high dynamic range.
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3.发明授权Photodiode CMOS imager with column-feedback soft-reset for imaging under ultra-low illumination and with high dynamic range 有权光电二极管CMOS成像器，具有柱反馈软复位，可在超低照度和高动态范围内成像公开(公告)号：US07746383B2
公开(公告)日：2010-06-29
申请号：US10779144
申请日：2004-02-12
申请人： Bedabrata Pain , Thomas J. Cunningham , Bruce Hancock , Suresh Seshadri , Monico Ortiz , Guang Yang
发明人： Bedabrata Pain , Thomas J. Cunningham , Bruce Hancock , Suresh Seshadri , Monico Ortiz , Guang Yang
摘要： The present invention provides a CMOS imager with a reset scheme, by which a CMOS imager generates a sub-kTC noise so that read noise does not depend on the sense node capacitance. By using a column feedback circuit, reset noise can be suppressed to a negligible amount so that photogate APS or CCD-like circuits can achieve noise performance to very efficient value. This scheme allows increasing sense node capacitance without increasing the noise and also achieves a large full-well value without sacrificing read noise performance. The feedback circuit in one of the embodiment of the present invention is located at the column side of the circuit. This design provides a minimal change to the pixel. As a result quantum efficiency or pixel size is not compromised. The present invention allows a CMOS imager to capture scene with high intra-scene contracts under low illumination with high dynamic range.
摘要翻译： 本发明提供了具有复位方案的CMOS成像器，CMOS成像器通过该方法产生子kTC噪声，使得读取噪声不依赖于感测节点电容。 通过使用列反馈电路，可以将复位噪声抑制到可忽略的量，使得光栅APS或类CCD电路可以实现非常有效的噪声性能。 该方案允许增加感测节点电容，而不增加噪声，并且还可以实现大的全阱值而不牺牲读取噪声性能。 本发明实施例之一的反馈电路位于电路的列侧。 此设计为像素提供了最小的变化。 因此量子效率或像素大小不会受到影响。 本发明允许CMOS成像器在具有高动态范围的低照度下捕获具有高的场景内契约的场景。
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公开(公告)号：US07215175B1
公开(公告)日：2007-05-08
申请号：US10932162
申请日：2004-09-01
CPC分类号： G11C17/18
摘要： An improved circuit for sensing and programming fuses in integrated circuits. The circuit is broadly comprised of a fuse cell, a reference circuit, a sense amplifier and a level detector. In one embodiment of the present invention, a two-stage sensing scheme is implemented. The improved fuse sensing circuit uses current-mode sensing and implements an auto-read current reduction scheme. Using a level-detect circuit, the virtual ground is raised automatically if the high-voltage power supply exceeds core supply (Vdd) by a fixed dc voltage. This reduces effective sensing voltage and the read current and thus helps preserve unblown fuse integrity. In one embodiment of the invention, four modes of operation are implemented: “Normal Read,” “Unblown_Read,” “Blown_Read_1” and “Blown_Read_2.” The default read mode is the “normal read” while the “Unblown” and “Blown” read modes are for fuse calibration purposes. In the “Unblown_Read” read mode, the circuit is operable to compare the fuse resistance against a lower reference resistance, closer to an unblown fuse resistance value, in order to make the comparison more stringent. Similarly, the “Blown_Read_1” and “Blown_Read_2” modes allow a more stringent comparison for a blown fuse resistance.
摘要翻译： 一种用于在集成电路中感测和编程保险丝的改进电路。 该电路广泛地包括熔丝单元，参考电路，读出放大器和电平检测器。 在本发明的一个实施例中，实现了两级感测方案。 改进的熔丝感测电路使用电流模式感测并实现自动读取电流降低方案。 使用电平检测电路，如果高压电源以固定的直流电压超过磁芯电源（Vdd），则虚拟接地将自动升高。 这降低了有效的感测电压和读取电流，从而有助于保持未熔断的保险丝完整性。 在本发明的一个实施例中，实现了四种操作模式：“Normal Read”，“Unblown_Read”，“Blown_Read_1”和“Blown_Read_2”。 “Unblown”和“Blown”读取模式的默认读取模式是“正常读取”，用于保险丝校准。 在“Unblown_Read”读取模式下，该电路可操作以将熔丝电阻与较低的参考电阻进行比较，更接近未熔断的保险丝电阻值，以使比较更加严格。 类似地，“Blown_Read_1”和“Blown_Read_2”模式允许对熔断熔断器电阻进行更严格的比较。
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公开(公告)号：US08481907B2
公开(公告)日：2013-07-09
申请号：US12009595
申请日：2008-01-18
申请人： Suresh Seshadri , David Cole , Roger M Smith , Bruce R. Hancock
发明人： Suresh Seshadri , David Cole , Roger M Smith , Bruce R. Hancock
CPC分类号： H04N17/004 , G09G3/006 , G09G2320/0209 , G09G2320/0219 , H04N5/2256 , H04N5/378
摘要： The effects of inter pixel capacitance in a pixilated array may be measured by first resetting all pixels in the array to a first voltage, where a first image is read out, followed by resetting only a subset of pixels in the array to a second voltage, where a second image is read out, where the difference in the first and second images provide information about the inter pixel capacitance. Other embodiments are described and claimed.
摘要翻译： 像素化阵列中的像素间电容的影响可以通过首先将阵列中的所有像元复位到第一电压来测量，其中读出第一图像，然后仅将阵列中的像素的子集重置为第二电压， 其中读出第二图像，其中第一和第二图像中的差异提供关于像素间电容的信息。 描述和要求保护其他实施例。
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公开(公告)号：US20100020099A1
公开(公告)日：2010-01-28
申请号：US12009595
申请日：2008-01-18
申请人： Suresh Seshadri , David Cole , Roger M. Smith , Bruce R. Hancock
发明人： Suresh Seshadri , David Cole , Roger M. Smith , Bruce R. Hancock
IPC分类号： G09G5/00
CPC分类号： H04N17/004 , G09G3/006 , G09G2320/0209 , G09G2320/0219 , H04N5/2256 , H04N5/378
摘要： The effects of inter pixel capacitance in a pixilated array may be measured by first resetting all pixels in the array to a first voltage, where a first image is read out, followed by resetting only a subset of pixels in the array to a second voltage, where a second image is read out, where the difference in the first and second images provide information about the inter pixel capacitance. Other embodiments are described and claimed.
摘要翻译： 像素化阵列中的像素间电容的影响可以通过首先将阵列中的所有像元复位到第一电压来测量，其中读出第一图像，然后仅将阵列中的像素的子集重置为第二电压， 其中读出第二图像，其中第一和第二图像中的差异提供关于像素间电容的信息。 描述和要求保护其他实施例。
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公开(公告)号：US07134057B1
公开(公告)日：2006-11-07
申请号：US10778916
申请日：2004-02-13
申请人： Pradeep Kaushik , Dennis Wendell , Suresh Seshadri
发明人： Pradeep Kaushik , Dennis Wendell , Suresh Seshadri
IPC分类号： G01C29/00
CPC分类号： G11C29/808 , G11C29/802 , G11C29/848
摘要： An apparatus and method for controlling and providing off-pitch shifting circuitry for implementing column redundancy in a multiple-array memory is described in connection with an on-board cache memory integrated with a microprocessor. Depending upon the particular sub-array being accessed, shift position data is provided to a shared, off-pitch shift circuit to control the read and/or write operations for the memory. A register bank stores data identifying the defective columns which is compared to the incoming address information to detect any matches. In response to a match, control information is provided to the off-pitch shift circuit for shifting or re-routing the incoming data to a non-defective address in the memory. In this way, defective columns located in different positions in each sub-array can be replaced by redundant paths, thereby repairing the cache and increasing the manufacturing yield of microprocessors with an on-board cache memory.
摘要翻译： 结合与微处理器集成的车载高速缓冲存储器来描述用于控制和提供用于实现多阵列存储器中的列冗余的偏移移位电路的装置和方法。 根据所访问的特定子阵列，将移位位置数据提供给共享的偏移移位电路以控制存储器的读取和/或写入操作。 寄存器组存储识别与输入地址信息进行比较的缺陷列的数据，以检测任何匹配。 响应于匹配，将控制信息提供给偏移移位电路，用于将输入数据移位或重新路由到存储器中的无缺陷地址。 以这种方式，位于每个子阵列中不同位置的有缺陷的列可以由冗余路径代替，由此修复高速缓存并且通过机载缓存存储器增加微处理器的制造产量。
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