Forward progress mechanism for stores in the presence of load contention in a system favoring loads
    2.
    发明授权
    Forward progress mechanism for stores in the presence of load contention in a system favoring loads 有权
    在有利于负载的系统中存在负载争用的商店的前进进度机制

    公开(公告)号:US08793442B2

    公开(公告)日:2014-07-29

    申请号:US13368958

    申请日:2012-02-08

    IPC分类号: G06F12/00

    CPC分类号: G06F12/0897 G06F12/0811

    摘要: A multiprocessor data processing system includes a plurality of cache memories including a cache memory. In response to the cache memory detecting a storage-modifying operation specifying a same target address as that of a first read-type operation being processed by the cache memory, the cache memory provides a retry response to the storage-modifying operation. In response to completion of the read-type operation, the cache memory enters a referee mode. While in the referee mode, the cache memory temporarily dynamically increases priority of any storage-modifying operation targeting the target address in relation to any second read-type operation targeting the target address.

    摘要翻译: 多处理器数据处理系统包括包括高速缓存存储器的多个高速缓存存储器。 响应于高速缓冲存储器检测指定与由高速缓冲存储器处理的第一读取型操作相同的目标地址的存储修改操作,高速缓冲存储器为存储修改操作提供重试响应。 响应于完成读取型操作,缓存存储器进入裁判模式。 在裁判模式下,高速缓存存储器临时动态地增加针对目标地址的任何存储修改操作的优先级,这相对于针对目标地址的任何第二读取类型操作。