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公开(公告)号：US09619390B2
公开(公告)日：2017-04-11
申请号：US12649548
申请日：2009-12-30
IPC分类号： G06F12/02 , G06F12/0862 , G06F12/0815
CPC分类号： G06F12/0862 , G06F12/0815
摘要： According to a method of data processing, a memory controller receives a plurality of data prefetch requests from multiple processor cores in the data processing system, where the plurality of prefetch load requests include a data prefetch request issued by a particular processor core among the multiple processor cores. In response to receipt of the data prefetch request, the memory controller provides a coherency response indicating an excess number of data prefetch requests. In response to the coherency response, the particular processor core reduces a rate of issuance of data prefetch requests.
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公开(公告)号：US09176876B2
公开(公告)日：2015-11-03
申请号：US13445646
申请日：2012-04-12
申请人： Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams , Thomas R. Puzak
发明人： Guy L. Guthrie , William J. Starke , Jeffrey A. Stuecheli , Derek E. Williams , Thomas R. Puzak
CPC分类号： G06F12/0811 , G06F12/12
摘要： A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.
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公开(公告)号：US08856455B2
公开(公告)日：2014-10-07
申请号：US13433022
申请日：2012-03-28
申请人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
发明人： Sanjeev Ghai , Guy L. Guthrie , William J. Starke , Jeff A. Stuecheli , Derek E. Williams , Phillip G. Williams
CPC分类号： G06F12/0815 , G06F12/0804 , G06F12/0817 , G06F12/0897 , G06F12/126
摘要： A data processing system includes a processor core supported by upper and lower level caches. In response to executing a deallocate instruction in the processor core, a deallocation request is sent from the processor core to the lower level cache, the deallocation request specifying a target address associated with a target cache line. In response to receipt of the deallocation request at the lower level cache, a determination is made if the target address hits in the lower level cache. In response to determining that the target address hits in the lower level cache, the target cache line is retained in a data array of the lower level cache and a replacement order field in a directory of the lower level cache is updated such that the target cache line is more likely to be evicted from the lower level cache in response to a subsequent cache miss.
摘要翻译： 数据处理系统包括由上层和下层高速缓存支持的处理器核心。 响应于在处理器核心中执行取消分配指令，从处理器核心向下级高速缓存发送解除分配请求，所述释放请求指定与目标高速缓存行相关联的目标地址。 响应于在较低级别高速缓存处接收到解除分配请求，确定目标地址是否在较低级别高速缓存中。 为了响应于确定目标地址在较低级别高速缓存中的命中，目标高速缓存行被保留在较低级别高速缓存的数据阵列中，并且更新下级高速缓存的目录中的替换顺序字段，使得目标高速缓存 线路可能会响应于后续的高速缓存未命中而从较低级别的缓存中逐出。
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4.发明申请REWIND ONLY TRANSACTIONS IN A DATA PROCESSING SYSTEM SUPPORTING TRANSACTIONAL STORAGE ACCESSES 有权支持交易存储访问的数据处理系统中的只有交易公开(公告)号：US20140040551A1
公开(公告)日：2014-02-06
申请号：US13650422
申请日：2012-10-12
IPC分类号： G06F12/08
CPC分类号： G06F12/0833 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/467 , G06F12/0811 , G06F2212/1024
摘要： In a multiprocessor data processing system having a distributed shared memory system, a memory transaction that is a rewind-only transaction (ROT) and that includes one or more transactional memory access instructions and a transactional abort instruction is executed. In response to execution of the one or more transactional memory access instructions, one or more memory accesses to the distributed shared memory system indicated by the one or more transactional memory access instructions are performed. In response to execution of the transactional abort instruction, execution results of the one or more transaction memory access instructions are discarded and control is passed to a fail handler.
摘要翻译： 在具有分布式共享存储器系统的多处理器数据处理系统中，执行作为倒退事务（ROT）并且包括一个或多个事务存储器访问指令和事务中止指令的存储器事务。 响应于执行一个或多个事务存储器访问指令，执行由一个或多个事务存储器访问指令指示的对分布式共享存储器系统的一个或多个存储器访问。 响应于事务中止指令的执行，一个或多个事务存储器访问指令的执行结果被丢弃，并且控制被传递给失败处理程序。
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公开(公告)号：US08645640B2
公开(公告)日：2014-02-04
申请号：US13166054
申请日：2011-06-22
申请人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory S. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
发明人： Michael S. Floyd , Guy L. Guthrie , Karthick Rajamani , Gregory S. Still , Jeffrey A. Stuecheli , Malcolm S. Ware
IPC分类号： G06F12/00
CPC分类号： G06Q50/10
摘要： An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.
摘要翻译： 公开了一种用于在具有多个小灯的数据处理系统内提供系统存储器使用限制的装置。 该装置包括系统存储器，存储器访问收集模块，存储器信用计费模块和存储器调节计数器。 存储器访问收集模块从小数点内的第一高速缓冲存储器接收来自第一高速缓冲存储器的第一组信号和来自第二高速缓冲存储器的第二组信号。 存储器信用计费模块根据从小巧的第一和第二高速缓存存储器的第一和第二组信号中提取的高速缓存访问的结果来跟踪每用户虚拟分区上的系统存储器的使用情况。 存储器油门计数器用于提供节气门控制信号，以防止当系统存储器使用量超过预定值时对系统存储器的访问。
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6.发明授权公开(公告)号：US08645633B2
公开(公告)日：2014-02-04
申请号：US13109249
申请日：2011-05-17
IPC分类号： G06F12/00
CPC分类号： G06F12/145 , G06F9/4552 , G06F12/1045 , G06F2212/1008
摘要： Fine-grained detection of data modification of original data is provided by associating separate guard bits with granules of memory storing the original data from which translated data has been obtained. The guard bits facilitate indicating whether the original data stored in the associated granule is indicated as protected. The guard bits are set and cleared by special-purpose instructions. Responsive to initiating a data store operation to modify the original data, the associated guard bit(s) are checked to determine whether the original data is indicated as protected. Responsive to the checking indicating that a guard bit is set for the associated original data, the data store operation to modify the original data is faulted and the translated data is discarded, thereby facilitating data coherency between the original data and the translated data.
摘要翻译： 通过将单独的保护位与存储已经获得翻译数据的原始数据的存储器的颗粒相关联来提供原始数据的数据修改的细粒度检测。 保护位有助于指示存储在相关联的颗粒中的原始数据是否被指示为受保护的。 保护位通过专用指令进行设置和清除。 响应于启动数据存储操作以修改原始数据，检查相关联的保护位以确定原始数据是否被指示为受保护的。 响应于指示为相关联的原始数据设置了保护位的检查，修改原始数据的数据存储操作发生故障，并且转换的数据被丢弃，从而促进原始数据和转换的数据之间的数据一致性。
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7.发明申请AGGREGATE DATA PROCESSING SYSTEM HAVING MULTIPLE OVERLAPPING SYNTHETIC COMPUTERS 有权具有多重叠加合成计算机的综合数据处理系统公开(公告)号：US20120324189A1
公开(公告)日：2012-12-20
申请号：US13599856
申请日：2012-08-30
IPC分类号： G06F12/14
CPC分类号： G06F12/0813 , G06F12/0284 , G06F15/167
摘要： A first SMP computer has first and second processing units and a first system memory pool, a second SMP computer has third and fourth processing units and a second system memory pool, and a third SMP computer has at least fifth and sixth processing units and third, fourth and fifth system memory pools. The fourth system memory pool is inaccessible to the third, fourth and sixth processing units and accessible to at least the second and fifth processing units, and the fifth system memory pool is inaccessible to the first, second and sixth processing units and accessible to at least the fourth and fifth processing units. A first interconnect couples the second processing unit for load-store coherent, ordered access to the fourth system memory pool, and a second interconnect couples the fourth processing unit for load-store coherent, ordered access to the fifth system memory pool.
摘要翻译： 第一SMP计算机具有第一和第二处理单元和第一系统存储器池，第二SMP计算机具有第三和第四处理单元和第二系统存储器池，并且第三SMP计算机具有至少第五和第六处理单元，第三SMP计算机具有至少第五和第六处理单元， 第四和第五系统内存池。 第四系统存储器池对于第三，第四和第六处理单元是不可访问的，并且可访问至少第二和第五处理单元，并且第五系统存储器池对于第一，第二和第六处理单元是不可访问的，并且至少可访问 第四和第五处理单元。 第一互连耦合第二处理单元，用于对第四系统存储池进行加载存储相关的有序访问，并且第二互连耦合第四处理单元，用于加载存储相关的有序访问到第五系统存储池。
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8.发明申请公开(公告)号：US20120297109A1
公开(公告)日：2012-11-22
申请号：US13109249
申请日：2011-05-17
IPC分类号： G06F12/08
CPC分类号： G06F12/145 , G06F9/4552 , G06F12/1045 , G06F2212/1008
摘要： Fine-grained detection of data modification of original data is provided by associating separate guard bits with granules of memory storing the original data from which translated data has been obtained. The guard bits facilitate indicating whether the original data stored in the associated granule is indicated as protected. The guard bits are set and cleared by special-purpose instructions. Responsive to initiating a data store operation to modify the original data, the associated guard bit(s) are checked to determine whether the original data is indicated as protected. Responsive to the checking indicating that a guard bit is set for the associated original data, the data store operation to modify the original data is faulted and the translated data is discarded, thereby facilitating data coherency between the original data and the translated data.
摘要翻译： 通过将单独的保护位与存储已经获得翻译数据的原始数据的存储器的颗粒相关联来提供原始数据的数据修改的细粒度检测。 保护位有助于指示存储在相关联的颗粒中的原始数据是否被指示为受保护的。 保护位通过专用指令进行设置和清除。 响应于启动数据存储操作以修改原始数据，检查相关联的保护位以确定原始数据是否被指示为受保护的。 响应于指示为相关联的原始数据设置了保护位的检查，修改原始数据的数据存储操作发生故障，并且转换的数据被丢弃，从而促进原始数据和转换的数据之间的数据一致性。
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公开(公告)号：US08205024B2
公开(公告)日：2012-06-19
申请号：US11560619
申请日：2006-11-16
CPC分类号： G06F15/173
摘要： In a data processing system, a plurality of agents communicate operations therebetween. Each operation includes a request and a combined response representing a system-wide response to the request. Latencies of requests and combined responses between the plurality of agents are observed. Each of the plurality of agents is configured with a respective duration of a protection window extension by reference to the observed latencies. Each protection window extension is a period following receipt of a combined response during winch an associated one of the plurality of agents protects transfer of coherency ownership of a data granule between agents. The plurality of agents employing protection window extensions in accordance with the configuration, and at least two of the agents have protection window extensions of differing durations.
摘要翻译： 在数据处理系统中，多个代理之间进行通信。 每个操作包括一个请求和组合的响应，代表对该请求的全系统响应。 观察到请求的延迟和多个代理之间的组合响应。 通过参考所观察到的延迟，多个代理中的每个被配置有保护窗口扩展的相应持续时间。 每个保护窗口扩展是在绞盘期间接收到组合响应之后的周期，多个代理之一相关联的一个代理保护代理之间的数据粒子的一致性所有权的传送。 多个代理根据配置使用保护窗口扩展，并且至少两个代理具有不同持续时间的保护窗口扩展。
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公开(公告)号：US08103791B2
公开(公告)日：2012-01-24
申请号：US12195130
申请日：2008-08-20
申请人： Benjiman L. Goodman , Guy L. Guthrie , Praveen S. Reddy , William J. Starke , Jeffrey A. Stuecheli
发明人： Benjiman L. Goodman , Guy L. Guthrie , Praveen S. Reddy , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F15/173 , G06F12/00 , G06F13/14 , G06F1/04 , G06F1/12
CPC分类号： G06F15/16
摘要： A data processing system includes a plurality of processing units, including at least a local master and a local hub, which are coupled for communication via a communication link. The local master includes a master capable of initiating an operation, a snooper capable of receiving an operation, and interconnect logic coupled to a communication link coupling the local master to the local hub. The interconnect logic includes request logic that synchronizes internal transmission of a request of the master to the snooper with transmission, via the communication link, of the request to the local hub.
摘要翻译： 数据处理系统包括多个处理单元，至少包括本地主站和本地集线器，其经由通信链路进行通信。 本地主机包括能够启动操作的主机，能够接收操作的监听器，以及耦合到将本地主机耦合到本地集线器的通信链路的逻辑互连。 互连逻辑包括请求逻辑，其将主机的请求的内部传输与通过通信链路传送到本地集线器的请求同步到窥探者的请求逻辑。
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