公开(公告)号：US08300196B2

公开(公告)日：2012-10-30

申请号：US11952574

申请日：2007-12-07

Applicant: Gyu-su Lee

Inventor： Gyu-su Lee

IPC: G02F1/1345

CPC classification number: G02F1/13452 ,  G09G3/3611 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2320/0223

Abstract: A film-chip complex includes a film which includes a connection region along one side, a chip which is mounted on the film, a gate signal line which is disposed on the film, wherein the gate signal line includes a gate lead which is disposed in the connection region and a gate main line which connects the chip with the gate lead and a signal line which is disposed on the film, wherein the signal line includes a signal lead which is disposed in the connection region, a signal main line which extends substantially toward an exterior of the connection region and a signal pad which is connected with the signal main line.

Abstract translation: 薄膜芯片复合体包括膜，其包括沿着一侧的连接区域，安装在膜上的芯片，设置在膜上的栅极信号线，其中栅极信号线包括设置在栅极引线上的栅极引线 所述连接区域和连接所述芯片与所述栅极引线的栅极主线和设置在所述膜上的信号线，其中，所述信号线包括设置在所述连接区域中的信号引线，基本上延伸的信号主线 朝向连接区域的外部和与信号主线连接的信号焊盘。

公开(公告)号：US5940059A

公开(公告)日：1999-08-17

申请号：US808340

申请日：1997-02-28

Applicant: Gyu-su Lee ,  Dong-gyu Kim

Inventor： Gyu-su Lee ,  Dong-gyu Kim

IPC: G02F1/136 ,  G09G3/36

CPC classification number: G09G3/36 ,  G09G2300/08 ,  G09G2320/0223

Abstract: Liquid crystal display devices include a first row of viewable liquid crystal display cells having data inputs electrically connected to a plurality of data lines (D1-Dn), control gates commonly connected to a first gate line (e.g., G1) and storage capacitors (Cst) having first electrodes electrically connected to a zeroth gate line (e.g., G0). A second row of viewable liquid crystal display cells are also provided having data inputs electrically connected to a plurality of data lines (D1-Dn), control gates commonly connected to a second gate line (e.g., G2) and storage capacitors (Cst) having first electrodes electrically connected to a first gate line (e.g., G1). Moreover, to maintain the RC delay value of the zeroth gate line at a level equal to the RC delay values associated with the higher order gate lines (e.g., G1-Gn), a row of nonviewable or "dummy" liquid crystal display cells are provided having data inputs electrically connected to the plurality of data lines, control gates commonly connected to the zeroth gate line and storage capacitors having first electrodes electrically coupled together. This row of nonviewable cells are provided to "mimic" a row of viewable cells so that the RC delay values associated with the zeroth gate line equals the RC delay value associated with the other gate lines in the array. The row of nonviewable cells may also be replaced by a variable resistance device (e.g., potentiometer, resistor ladder, etc.) and a variable capacitance device which are electrically coupled in series between the zeroth gate line and respective reference potentials (e.g., Vcom, GND, etc.). These variable devices are adjusted so that the total effective RC delay values associated with the zeroth gate line equals the RC delay value associated with the other gate lines.

Abstract translation: 液晶显示装置包括具有电连接到多个数据线（D1-Dn）的数据输入的第一排可见液晶显示单元，公共连接到第一栅极线（例如G1）和存储电容器（Cst）的控制栅极 ）具有电连接到第零栅极线（例如，G0）的第一电极。 还提供了第二排可见液晶显示单元，其具有电连接到多条数据线（D1-Dn）的数据输入端，公共连接到第二栅极线（例如G2）的控制栅极和具有 电连接到第一栅极线（例如，G1）的第一电极。 此外，为了将第零极栅极线的RC延迟值保持在与高阶栅极线（例如G1-Gn）相关联的RC延迟值的电平上，一行不可视或“虚拟”液晶显示单元是 提供有数据输入电连接到多条数据线，公共连接到第零栅极线的控制栅极和具有电耦合在一起的第一电极的存储电容器。 提供这行不可见单元格以“模拟”一行可视单元，使得与第零门线相关联的RC延迟值等于与阵列中的其他栅极线相关联的RC延迟值。 不可见单元的行也可以由可变电阻器件（例如，电位器，电阻梯等）和可变电容器件替代，该可变电容器件在第零栅极线和相应的参考电位之间串联电耦合（例如，Vcom， GND等）。 调整这些可变装置，使得与第零门线相关联的总有效RC延迟值等于与其它栅极线相关联的RC延迟值。