SHIFT REGISTER UNIT, SHIFT REGISTER CIRCUIT AND DRIVING METHOD, AND DISPLAY PANEL

    公开(公告)号:US20210142712A1

    公开(公告)日:2021-05-13

    申请号:US16075119

    申请日:2017-11-15

    IPC分类号: G09G3/20 G11C19/28

    摘要: A shift register unit includes: an input circuit, a reset circuit, and an output circuit; a first pull-down control circuit, configured to transmit the first power signal to the first and second pull-down control nodes, and the pull-down node according to the pull-up node, a second pull-down control circuit, configured to transmit a second power signal to the first pull-down control node according to the second power signal, transmit the second power signal to the second pull-down control node according to the first pull-down control node, and transmit the second power signal to the pull-down node according to the second pull-down control node, and a pull-down circuit, configured to transmit the first power signal to the pull-up node and the signal output end according to the pull-down node. The present disclosure may ensure the normal output of the signal and improve the ability of reducing noise.

    Shift-register circuit, a driving method thereof, and related display apparatus

    公开(公告)号:US10991332B2

    公开(公告)日:2021-04-27

    申请号:US16614486

    申请日:2018-01-16

    IPC分类号: G09G3/36 G09G3/3266

    摘要: The present application discloses a shift-register circuit including a shift-register unit and a shutdown-discharge sub-circuit. The shift-register unit is coupled to a clock port, a first reference voltage port, a second reference voltage port, and an output port and configured to set a voltage level at a pull-up node to control a clock signal from the clock port being outputted to the output port to drive a display panel during a display period. The shutdown discharge sub-circuit is configured to at least simultaneously receive a shutdown signal at a first voltage level from a shutdown-discharge control port and a second signal at the first voltage level from the second reference voltage port to start a shutdown period to discharge at least one of the pull-up node and the output port. The shutdown signal has a signal length longer than a signal length of the second signal.

    Shift register, method for driving the same, gate driving circuit, and display device

    公开(公告)号:US10950196B2

    公开(公告)日:2021-03-16

    申请号:US16077369

    申请日:2018-02-12

    IPC分类号: G09G3/36 G11C19/28

    摘要: A shift register, a method for driving the same, a gate driving circuit, and a display device are described. The shift register includes a pull-up control circuit which outputs the voltage of a signal input terminal, a pull-up circuit which outputs the voltage of a first clock signal input terminal, a pull-down control circuit which outputs the voltage of a second clock signal input terminal, or pulls down the voltage of the pull-down node, a pull-down circuit which pulls down voltages of the pull-up node and the signal output terminal to the first voltage terminal, respectively, a reset circuit which pulls down voltages of the pull-up node and the signal output terminal to the first voltage terminal, respectively, and a noise reduction control circuit which outputs the voltage of a noise reduction control signal terminal to the pull-down node in the blanking time of an image frame.

    METHOD OF PREVENTING FALSE OUTPUT OF GOA CIRCUIT OF A LIQUID CRYSTAL DISPLAY PANEL

    公开(公告)号:US20210174758A1

    公开(公告)日:2021-06-10

    申请号:US15777591

    申请日:2017-06-07

    IPC分类号: G09G3/36

    摘要: The present application discloses a method for preventing false output of a GOA circuit in a display panel. The method includes providing N clock signals respectively to N GOA units in each of M groups of GOA units cascaded in series. The N clock signals are outputted time-sequentially from a 1st clock signal to a N-th clock signal. The method additionally includes counting a first total number of pulses of the 1st clock signal and a second total number of pulses of the N-th clock signal, comparing each of them to M, and generating a reset signal based on a determination that at least one of the first total number of pulses and the second total number of pulses is smaller than M. The method furthermore includes releasing residual charges of the GOA circuit without outputting any gate-driving signal for a duration of time.

    Shift register unit, gate driving circuit, display apparatus and control method

    公开(公告)号:US10978017B2

    公开(公告)日:2021-04-13

    申请号:US16335814

    申请日:2018-07-19

    IPC分类号: G09G3/36 G11C19/28

    摘要: There is provided in the present disclosure a shift register unit, including: an input sub-circuit, whose first terminal is coupled to an input signal terminal, and second terminal is coupled to a pull-up node; an output sub-circuit, whose first terminal is coupled to the pull-up node, second terminal is coupled to a clock signal terminal, and third terminal is coupled to an output terminal, and configured to output a clock signal of the clock signal terminal to the output terminal under the control of a level signal of the pull-up node; a first electro-static discharge sub-circuit, whose first terminal is coupled to the pull-up node, second terminal is coupled to an electro-static discharge control terminal, and third terminal is coupled to a ground, and configured to discharge static electricity accumulated at the pull-up node under the control of a level signal of the electro-static discharge control terminal.

    Display panel and common voltage compensation method thereof and display device

    公开(公告)号:US10529297B2

    公开(公告)日:2020-01-07

    申请号:US15765535

    申请日:2017-09-01

    IPC分类号: G09G3/36

    摘要: The present disclosure provides a display panel, a method for compensating a common voltage thereof, and a display device, belongs to the field of display technology and can solve the problem that the existing display panel cannot effectively compensate the common voltage in the middle region thereof. The display panel includes a plurality of compensation regions, each of the compensation regions is provided with a plurality of common electrodes. The display panel includes a compensation circuit corresponding to each compensation region. The compensation circuit may compensate an actual common voltage of the common electrode in a corresponding compensation region, according to an average value of a difference between an actual common voltage and a preset common voltage of each common electrode in the corresponding compensation region.