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公开(公告)号：US11100841B2
公开(公告)日：2021-08-24
申请号：US16066729
申请日：2017-10-10
发明人： Hongjun Wang
IPC分类号： G09G3/20
摘要： A shift register, a driving method thereof, a gate driving circuit, and a display device. The shift register includes an input sub-circuit, a reset sub-circuit, a node control sub-circuit, a potential maintenance sub-circuit, a first output sub-circuit, and a second output sub-circuit.
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公开(公告)号：US10789904B2
公开(公告)日：2020-09-29
申请号：US16702515
申请日：2019-12-03
发明人： Yuanyuan Liu , Shuai Liu , Xuanxuan Qiao , Xianfeng Yuan , Hongjun Wang , Kangxi Chen , Min Wang , Min Zhong
IPC分类号： G09G3/36
摘要： A method and a device for driving a display panel, and a display device are provided. The method includes: dividing the display panel into at least two display regions, where each display region corresponds to a timing controller, and the timing controller is configured to control the corresponding display region to display; dividing each display region into multiple detection blocks; detecting whether a defect block exists in each display region; and enabling, when the defect block exists in only one display region, by the timing controller corresponding to the only one display region, a pattern detection function, and enabling, when the defect block exists in each of more than one display region, by the timing controllers corresponding to the more than one display region simultaneously, the pattern detection function.
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公开(公告)号：US20210174758A1
公开(公告)日：2021-06-10
申请号：US15777591
申请日：2017-06-07
发明人： Yuanyuan Liu , Jianjun Wang , Hongjun Wang , Min Wang , Rui Ma
IPC分类号： G09G3/36
摘要： The present application discloses a method for preventing false output of a GOA circuit in a display panel. The method includes providing N clock signals respectively to N GOA units in each of M groups of GOA units cascaded in series. The N clock signals are outputted time-sequentially from a 1st clock signal to a N-th clock signal. The method additionally includes counting a first total number of pulses of the 1st clock signal and a second total number of pulses of the N-th clock signal, comparing each of them to M, and generating a reset signal based on a determination that at least one of the first total number of pulses and the second total number of pulses is smaller than M. The method furthermore includes releasing residual charges of the GOA circuit without outputting any gate-driving signal for a duration of time.
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公开(公告)号：US20200251063A1
公开(公告)日：2020-08-06
申请号：US16702515
申请日：2019-12-03
发明人： Yuanyuan Liu , Shuai Liu , Xuanxuan Qiao , Xianfeng Yuan , Hongjun Wang , Kangxi Chen , Min Wang , Min Zhong
IPC分类号： G09G3/36
摘要： A method and a device for driving a display panel, and a display device are provided. The method includes: dividing the display panel into at least two display regions, where each display region corresponds to a timing controller, and the timing controller is configured to control the corresponding display region to display; dividing each display region into multiple detection blocks; detecting whether a defect block exists in each display region; and enabling, when the defect block exists in only one display region, by the timing controller corresponding to the only one display region, a pattern detection function, and enabling, when the defect block exists in each of more than one display region, by the timing controllers corresponding to the more than one display region simultaneously, the pattern detection function.
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公开(公告)号：US11169422B2
公开(公告)日：2021-11-09
申请号：US16639512
申请日：2019-08-19
发明人： Xuanxuan Qiao , Shuai Liu , Xianfeng Yuan , Hongjun Wang , Yuanyuan Liu , Min Wang
IPC分类号： G02F1/1343 , G02F1/1333 , G02F1/1335 , G02F1/1339 , G02F1/1341
摘要： A display panel is disclosed. The display panel includes a plurality of pixel structures, each of the pixel structures including: a first electrode being a transparent electrode; a second electrode in substantially parallel arrangement with respect to the first electrode; a retaining wall between the first electrode and the second electrode, and enclosing a sealed cavity together with the first electrode and the second electrode; and a target liquid in the sealed cavity containing a plurality of particles, and the plurality of particles being configured to form photonic crystals with different lattice spacing under an action of different electric fields between the first electrode and the second electrode.
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公开(公告)号：US11107430B2
公开(公告)日：2021-08-31
申请号：US15777591
申请日：2017-06-07
发明人： Yuanyuan Liu , Jianjun Wang , Hongjun Wang , Min Wang , Rui Ma
摘要： The present application discloses a method for preventing false output of a GOA circuit in a display panel. The method includes providing N clock signals respectively to N GOA units in each of M groups of GOA units cascaded in series. The N clock signals are outputted time-sequentially from a 1st clock signal to a N-th clock signal. The method additionally includes counting a first total number of pulses of the 1st clock signal and a second total number of pulses of the N-th clock signal, comparing each of them to M, and generating a reset signal based on a determination that at least one of the first total number of pulses and the second total number of pulses is smaller than M. The method furthermore includes releasing residual charges of the GOA circuit without outputting any gate-driving signal for a duration of time.
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公开(公告)号：US10726755B2
公开(公告)日：2020-07-28
申请号：US16332935
申请日：2018-05-31
发明人： Yuanyuan Liu , Xiaoshi Liu , Xianfeng Yuan , Hongjun Wang , Min Wang
摘要： A driving circuit, a control method thereof, a display panel, and a display device. The driving circuit comprises a logic board, a gate driving sub-circuit, and an interface control sub-circuit. The interface control sub-circuit is configured to detect a timing control signal outputted by the logic board to the gate driving sub-circuit via a signal transmission interface, and control the signal transmission interface of the logic board to stop outputting the timing control signal to the gate driving sub-circuit in response to detecting that the timing control signal does not satisfy a preset condition.
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8.发明申请公开(公告)号：US20200160492A1
公开(公告)日：2020-05-21
申请号：US16413087
申请日：2019-05-15
发明人： Xiaoshi Liu , Hongjun Wang
摘要： An image adjustment method and device, an image display method and device, and a non-transitory storage medium are disclosed. The image adjustment method includes: acquiring a saliency value of at least one pixel in an initial image; and performing a first brightness adjustment on a corresponding pixel in the at least one pixel in the initial image based on Weber's law.
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公开(公告)号：US10706760B2
公开(公告)日：2020-07-07
申请号：US16328384
申请日：2018-06-29
发明人： Kangxi Chen , Min Wang , Hui Dong , Hongjun Wang , Jianjun Wang
摘要： A shift register, a method for driving the same, a gate driver circuit, and a display device are provided. The shift register includes an input circuit, a reset circuit, a first control circuit, a first output circuit, and a second output circuit, where the first output circuit includes two output channels, where one channel is that under the joint control of signals of a first clock signal terminal and a first node, a signal of a first clock signal terminal is provided to a drive signal output terminal of the shift register, and the other channel is that under the joint control of signals of the second clock signal terminal and the first node, a signal of a second clock signal terminal is provided to the drive signal output terminal.
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公开(公告)号：US20200020264A1
公开(公告)日：2020-01-16
申请号：US16328384
申请日：2018-06-29
发明人： Kangxi Chen , Min Wang , Hui Dong , Hongjun Wang , Jianjun Wang
摘要： This disclosure discloses a shift register, a method for driving the same, a gate driver circuit, and a display device. The shift register includes an input circuit, a reset circuit, a first control circuit, a first output circuit, and a second output circuit, where the first output circuit includes two output channels, where one channel is that under the joint control of signals of a first clock signal terminal and a first node, a signal of a first clock signal terminal is provided to a drive signal output terminal of the shift register, and the other channel is that under the joint control of signals of the second clock signal terminal and the first node, a signal of a second clock signal terminal is provided to the drive signal output terminal, and the first output circuit cooperates with the other four circuits so that these two channels can operate alternately to thereby avoid current from flowing through only one of the channels so as to improve the service lifetime of the shift register.
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