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    Systems and methods for dynamically modifying coherence domains
    2.
    发明授权
    Systems and methods for dynamically modifying coherence domains 有权

    公开(公告)号：US10540286B2

    公开(公告)日：2020-01-21

    申请号：US15967596

    申请日：2018-04-30

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Dejan S Milojicic ,  Keith Packard ,  Michael S. Woodacre ,  Andrew R Wheeler

    IPC: G06F12/08 ,  G06F12/0837

    Abstract: Systems and methods for dynamically modifying coherence domains are discussed herein. In various embodiments, a hardware controller may be provided that is configured to automatically recognize application behavior and dynamically reconfigure coherence domains in hardware and software to tradeoff performance for reliability and scalability. Modifying the coherence domains may comprise repartitioning the system based on cache coherence independently of one or more software layers of the system. Memory-driven algorithms may be invoked to determine one or more dynamic coherence domain operations to implement. In some embodiments, declarative policy statements may be received from a user via one or more interfaces associated with the controller. The controller may be configured to dynamically adjust cache coherence policy based on the declarative policy statements received from the user.

    Capability enforcement processors
    6.
    发明授权
    Capability enforcement processors 有权

    公开(公告)号：US10884953B2

    公开(公告)日：2021-01-05

    申请号：US15693149

    申请日：2017-08-31

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Dejan S Milojicic ,  Chris I Dalton ,  Paolo Faraboschi ,  Kirk M Bresniker

    IPC: G06F12/14

    Abstract: Example implementations relate to a capability enforcement processor. In an example, a capability enforcement processor may be interposed between a memory that stores data accessible via capabilities and a system processor that executes processes. The capability enforcement processor intercepts a memory request from the system processor and enforces the memory request based on capability enforcement processor capabilities maintained in per-process capability spaces of the capability enforcement processor.

    SYSTEMS AND METHODS FOR AGGREGATE BANDWIDTH AND LATENCY OPTIMIZATION
    7.
    发明申请
    SYSTEMS AND METHODS FOR AGGREGATE BANDWIDTH AND LATENCY OPTIMIZATION 审中-公开

    公开(公告)号：US20190334771A1

    公开(公告)日：2019-10-31

    申请号：US15967583

    申请日：2018-04-30

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Dejan S Milojicic ,  Sharad Singhal ,  Andrew R. Wheeler ,  Michael S. Woodacre

    IPC: H04L12/24 ,  G06F11/34 ,  G06F11/30 ,  H04L12/26 ,  H04L12/911

    Abstract: Systems and methods for dynamically and programmatically controlling hardware and software to optimize bandwidth and latency across partitions in a computing system are discussed herein. In various embodiments, performance within a partitioned computing system may be monitored and used to automatically reconfigure the computing system to optimize aggregate bandwidth and latency. Reconfiguring the computing system may comprise reallocating hardware resources among partitions, programming firewalls to enable higher bandwidth for specific inter-partition traffic, switching programming models associated with individual partitions, starting additional instances of one or more applications running on the partitions, and/or one or more other operations to optimize the overall aggregate bandwidth and latency of the system.

    Modification of multiple lines of cache chunk before invalidation of lines
    8.
    发明授权
    Modification of multiple lines of cache chunk before invalidation of lines 有权

    公开(公告)号：US10241911B2

    公开(公告)日：2019-03-26

    申请号：US15246136

    申请日：2016-08-24

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Gabriel Parmer ,  Paolo Faraboschi ,  Dejan S Milojicic

    IPC: G06F12/0808 ,  G06F12/0831 ,  G06F12/0811

    Abstract: Examples described herein relate to caching in a system with multiple nodes sharing a globally addressable memory. The globally addressable memory includes multiple windows that each include multiple chunks. Each node of a set of the nodes includes a cache that is associated with one of the windows. One of the nodes includes write access to one of the chunks of the window. The other nodes include read access to the chunk. The node with write access further includes a copy of the chunk in its cache and modifies multiple lines of the chunk copy. After a first line of the chunk copy is modified, a notification is sent to the other nodes that the chunk should be marked dirty. After multiple lines are modified, an invalidation message is sent for each of the modified lines of the set of the nodes.

    Systems and methods for aggregate bandwidth and latency optimization
    9.
    发明授权
    Systems and methods for aggregate bandwidth and latency optimization 有权

    公开(公告)号：US11128531B2

    公开(公告)日：2021-09-21

    申请号：US15967583

    申请日：2018-04-30

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Dejan S Milojicic ,  Sharad Singhal ,  Andrew R. Wheeler ,  Michael S. Woodacre

    IPC: H04L12/24 ,  G06F11/34 ,  H04L12/911 ,  H04L12/26 ,  G06F11/30

    Abstract: Systems and methods for dynamically and programmatically controlling hardware and software to optimize bandwidth and latency across partitions in a computing system are discussed herein. In various embodiments, performance within a partitioned computing system may be monitored and used to automatically reconfigure the computing system to optimize aggregate bandwidth and latency. Reconfiguring the computing system may comprise reallocating hardware resources among partitions, programming firewalls to enable higher bandwidth for specific inter-partition traffic, switching programming models associated with individual partitions, starting additional instances of one or more applications running on the partitions, and/or one or more other operations to optimize the overall aggregate bandwidth and latency of the system.

    SERVER VIRTUAL ADDRESS SPACE
    10.
    发明申请
    SERVER VIRTUAL ADDRESS SPACE 审中-公开

    公开(公告)号：US20190095242A1

    公开(公告)日：2019-03-28

    申请号：US16083284

    申请日：2016-03-09

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Izzat El Hajj ,  Alexander Merritt ,  Gerd Zellweger ,  Dejan S Milojicic

    IPC: G06F9/48 ,  G06F12/10

    Abstract: Techniques for a thread in client process to switch to a server virtual address space are provided. In one aspect, a process may attach to a server virtual address space. A request may be received from a client thread within the client process to switch from a virtual address space associated with the client thread to a server virtual address space. The client thread may switch from the client thread associated virtual address space to the server virtual address space.

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