公开(公告)号：US10324644B2

公开(公告)日：2019-06-18

申请号：US15476185

申请日：2017-03-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Kaisheng Ma ,  Qiong Cai ,  Cong Xu ,  Paolo Faraboschi

IPC: G06F12/00 ,  G06F3/06 ,  G06F15/78 ,  G06F9/48 ,  G06F9/50

Abstract: Examples described herein include receiving an operation pipeline for a computing system and building a graph that comprises a model for a number of potential memory side accelerator thread assignments to carry out the operation pipeline. The computing system may comprise at least two memories and a number of memory side accelerators. Each model may comprise a number of steps and at least one step out of the number of steps in each model may comprise a function performed at one memory side accelerator out of the number of memory side accelerators. Examples described herein also include determining a cost of at least one model.

公开(公告)号：US20180285011A1

公开(公告)日：2018-10-04

申请号：US15476185

申请日：2017-03-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Kaisheng Ma ,  Qiong Cai ,  Cong Xu ,  Paolo Faraboschi

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/061 ,  G06F3/0683 ,  G06F9/4881 ,  G06F9/5044 ,  G06F15/7821

Abstract: Examples described herein include receiving an operation pipeline for a computing system and building a graph that comprises a model for a number of potential memory side accelerator thread assignments to carry out the operation pipeline. The computing system may comprise at least two memories and a number of memory side accelerators. Each model may comprise a number of steps and at least one step out of the number of steps in each model may comprise a function performed at one memory side accelerator out of the number of memory side accelerators. Examples described herein also include determining a cost of at least one model.