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公开(公告)号：US10387335B2
公开(公告)日：2019-08-20
申请号：US15718214
申请日：2017-09-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Dejan S. Milojicic , Moritz Josef Hoffmann , Alexander Richardson , Qiong Cai
IPC: G06F12/00 , G06F12/14 , G06F12/121 , G06F12/02
Abstract: In one example, a processor sends a memory access request including a data capability and a handle which references a master capability. In response to receiving the memory access request, a memory controller checks whether the handle references a valid master capability and checks whether the data capability is within a scope of the master capability. In response to determining that the master capability is valid and the data capability is within the scope of the master capability, the memory controller returns a result of the memory access request to the processor.
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公开(公告)号：US10725940B2
公开(公告)日：2020-07-28
申请号：US16167494
申请日：2018-10-22
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Qiong Cai , Paolo Faraboschi , Cong Xu , Ping Chi , Sai Rahul Chalamalasetti , Andrew C. Walton
Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.
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公开(公告)号：US10324644B2
公开(公告)日：2019-06-18
申请号：US15476185
申请日：2017-03-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Kaisheng Ma , Qiong Cai , Cong Xu , Paolo Faraboschi
Abstract: Examples described herein include receiving an operation pipeline for a computing system and building a graph that comprises a model for a number of potential memory side accelerator thread assignments to carry out the operation pipeline. The computing system may comprise at least two memories and a number of memory side accelerators. Each model may comprise a number of steps and at least one step out of the number of steps in each model may comprise a function performed at one memory side accelerator out of the number of memory side accelerators. Examples described herein also include determining a cost of at least one model.
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公开(公告)号：US20190056872A1
公开(公告)日：2019-02-21
申请号：US16167494
申请日：2018-10-22
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Qiong Cai , Paolo Faraboschi , Cong Xu , Ping Ping , Sai Rahul Chalamalasetti , Andrew C. Walton
Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.
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公开(公告)号：US20180336034A1
公开(公告)日：2018-11-22
申请号：US15597757
申请日：2017-05-17
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Craig Warner , Qiong Cai , Paolo Faraboschi , Gregg B Lesartre
IPC: G06F9/30 , G06F12/0804 , G06F12/0875 , G06F15/78 , G06F12/128
CPC classification number: G06F9/30185 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/30076 , G06F9/30181 , G06F12/0804 , G06F12/0875 , G06F12/128 , G06F15/7825 , G06F2212/452 , G06F2212/60 , G06F2212/69
Abstract: In one example in accordance with the present disclosure, a compute engine block may comprise a data port connecting a processing core to a data cache, wherein the data port receives requests for accessing a memory and a data communication pathway to enable servicing of data requests of the memory. The processing core may be configured to identify a value in a predetermined address range of a first data request and adjust the bit size of a load instruction used by the processing core when a first value is identified.
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Patent Agency Ranking
公开(公告)号：US10108351B2
公开(公告)日：2018-10-23
申请号：US15190276
申请日：2016-06-23
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Qiong Cai , Paolo Faraboschi , Cong Xu , Ping Chi , Sai Rahul Chalamalasetti , Andrew C. Walton
IPC: G06F3/06
Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.
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公开(公告)号：US11481328B2
公开(公告)日：2022-10-25
申请号：US16925870
申请日：2020-07-10
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Alexandros Daglis , Paolo Faraboschi , Qiong Cai , Gary Gostin
IPC: G06F12/08 , G06F12/0817 , G06F12/14 , G06F12/0831 , G06F12/0811
Abstract: A technique includes, in response to a cache miss occurring with a given processing node of a plurality of processing nodes, using a directory-based coherence system for the plurality of processing nodes to regulate snooping of an address that is associated with the cache miss. Using the directory-based coherence system to regulate whether the address is included in a snooping domain is based at least in part on a number of cache misses associated with the address.
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公开(公告)号：US10740235B2
公开(公告)日：2020-08-11
申请号：US15746465
申请日：2015-07-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Alexandros Daglis , Paolo Faraboschi , Qiong Cai , Gary Gostin
IPC: G06F12/08 , G06F12/0817 , G06F12/14 , G06F12/0831 , G06F12/0811
Abstract: A technique includes, in response to a cache miss occurring with a given processing node of a plurality of processing nodes, using a directory-based coherence system for the plurality of processing nodes to regulate snooping of an address that is associated with the cache miss. Using the directory-based coherence system to regulate whether the address is included in a snooping domain is based at least in part on a number of cache misses associated with the address.
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公开(公告)号：US20180285011A1
公开(公告)日：2018-10-04
申请号：US15476185
申请日：2017-03-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Kaisheng Ma , Qiong Cai , Cong Xu , Paolo Faraboschi
IPC: G06F3/06
CPC classification number: G06F3/0631 , G06F3/061 , G06F3/0683 , G06F9/4881 , G06F9/5044 , G06F15/7821
Abstract: Examples described herein include receiving an operation pipeline for a computing system and building a graph that comprises a model for a number of potential memory side accelerator thread assignments to carry out the operation pipeline. The computing system may comprise at least two memories and a number of memory side accelerators. Each model may comprise a number of steps and at least one step out of the number of steps in each model may comprise a function performed at one memory side accelerator out of the number of memory side accelerators. Examples described herein also include determining a cost of at least one model.
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公开(公告)号：US20170371561A1
公开(公告)日：2017-12-28
申请号：US15190276
申请日：2016-06-23
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Qiong Cai , Paolo Faraboschi , Cong Xu , Ping Chi , Sai Rahul Chalamalasetti , Andrew C. Walton
IPC: G06F3/06
Abstract: Techniques for reallocating a memory pending queue based on stalls are provided. In one aspect, it may be determined at a memory stop of a memory fabric that at least one class of memory access is stalled. It may also be determined at the memory stop of the memory fabric that there is at least one class of memory access that is not stalled. At least a portion of a memory pending queue may be reallocated from the class of memory access that is not stalled to the class of memory access that is stalled.
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