公开(公告)号：US20180239901A1

公开(公告)日：2018-08-23

申请号：US15752304

申请日：2015-09-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, LP

Inventor： JEFFREY KEVIN JEANSONNE ,  VALI ALI ,  DAVID PLAQUIN ,  MAUGAN VILLATEL

IPC: G06F21/57 ,  G06F9/4401 ,  G06F11/22 ,  G06F8/65

CPC classification number: G06F21/572 ,  G06F8/66 ,  G06F9/44 ,  G06F9/4401 ,  G06F11/22 ,  G06F11/3668 ,  G06F21/562 ,  G06F21/575

Abstract: Examples herein disclose a processor-based computing system. The system comprises at least one processor, a non-volatile memory comprising a basic input output system (BIOS), wherein the BIOS creates a data structure and sets up at least one verification software component executed by the processor, a controller communicatively linked to the at least one verification software component, and a memory comprising a system management memory coupled to the at least one processor and code which is executable by the processor-based system to cause the processor to validate the BIOS during a runtime of the processor-based system using the at least one verification software component and the controller.