公开(公告)号：US10719391B2

公开(公告)日：2020-07-21

申请号：US16329327

申请日：2017-04-28

申请人： HITACHI, LTD.

发明人： Kotoko Fujita ,  Masanori Fujii

IPC分类号： G06F11/00 ,  G06F11/10 ,  G06F3/06 ,  G06F13/28 ,  G06F13/16

摘要： Provided is a storage system that includes a first cluster and a second cluster and that controls a storage device. The first cluster has a first processor and a first memory, and the second cluster has a second processor and a second memory. The second processor includes an error check module for verifying a DMA controller and a guarantee code. The first cluster adds the guarantee code to write data and stores the same in the first memory. The second cluster activates the DMA controller, reads the write data and the guarantee code from the first memory, causes the error check module to verify the guarantee code, and then stores the same in the second memory.

公开(公告)号：US11232197B2

公开(公告)日：2022-01-25

申请号：US16568590

申请日：2019-09-12

申请人： Hitachi, Ltd.

发明人： Naoya Okamura ,  Takumi Tsujishita ,  Masanori Fujii

IPC分类号： H04L29/06 ,  G06F21/55 ,  G06F13/10 ,  G06F21/57

摘要： In a storage system including an FPGA having a logic which executes a prescribed processing and a plurality of devices coupled to the FPGA via a bus, the logic of the FPGA is configured to: attempt to access the plurality of devices and, based on a status of access to the devices, determine whether or not there is an abnormality in the access to the devices; and when it is determined that there is an abnormality in the access to a device, reset an IF unit for performing a communication processing via a bus of the device.

公开(公告)号：US10909007B2

公开(公告)日：2021-02-02

申请号：US16330333

申请日：2017-03-24

申请人： HITACHI, LTD.

发明人： Naoya Okamura ,  Masanori Fujii ,  Naoki Moritoki

IPC分类号： G06F11/00 ,  G06F11/20 ,  G06F3/06

摘要： Provided are a storage system and a storage control method wherein, when communication is disabled (communication via a data communication path is disabled) in spite of replacement of a second CTL among a first CTL and the second CTL that are redundant storage controllers and that are coupled via the data communication path, the first CTL executes a write process of writing dirty data and data management information to one or more storage devices while maintaining acceptance of I/O requests from a host. The replaced second CTL reads the data management information from the one or more storage devices. The first CTL stops accepting I/O requests from the host. The replaced second CTL starts accepting I/O requests from the host.