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公开(公告)号:US10725865B2
公开(公告)日:2020-07-28
申请号:US15548635
申请日:2015-02-25
申请人: HITACHI, LTD.
摘要: A storage unit includes a plurality of storage devices that form a RAID group, that are coupled to the same bus, and that communicate with each other. Each of the plurality of storage devices includes a device controller and a storage medium. The plurality of storage devices store each of data and parities generated on the basis of the data, the data and the parities being included in RAID stripes. A first device controller of a first storage device included in the RAID group transmits, to the plurality of storage devices included in the RAID group other than the first storage device, an instruction to transfer the data and/or the parities included in the RAID stripes and restores the data or the parity corresponding to the first storage device of the RAID stripes on the basis of the transferred data and the transferred parities.
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公开(公告)号:US10102070B2
公开(公告)日:2018-10-16
申请号:US15531795
申请日:2015-06-01
申请人: Hitachi, Ltd.
IPC分类号: G06F11/00 , G06F11/10 , G06F3/06 , G06F12/0804
摘要: A purpose is to speed up a write process with a parity update. An information processing system includes storage devices constituting a RAID group, coupled to one bus and communicating with each other. Each of the storage devices includes a device controller and a storage medium for storing data. The storage devices include a first storage device storing old data and a second storage device storing old parity associated with the old data. A first device controller of the first storage device creates intermediate parity based on the old data and new data for updating the old data and transmit the intermediate parity to the second storage device specifying the second storage device storing the old parity associated with the old data, and a second device controller of the second storage device creates new parity based on the intermediate parity and the old parity.
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公开(公告)号:US10467176B2
公开(公告)日:2019-11-05
申请号:US15545461
申请日:2015-02-25
申请人: Hitachi, Ltd.
IPC分类号: G06F13/42 , G06F3/06 , G06F13/00 , G06F13/10 , G06F13/12 , G06F13/14 , G06F12/02 , G06F13/40
摘要: An information processing device having a processor and memory, and including one or more accelerators and one or more storage devices, wherein: the information processing device has one network for connecting the processor, the accelerators, and the storage devices; the storage devices have an initialization interface for accepting an initialization instruction from the processor, and an I/O issuance interface for issuing an I/O command; and the processor notifies the accelerators of the address of the initialization interface or the address of the I/O issuance interface.
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公开(公告)号:US10310764B2
公开(公告)日:2019-06-04
申请号:US15518289
申请日:2014-11-04
申请人: Hitachi, Ltd.
摘要: The semiconductor memory device comprises a memory element group (one or more semiconductor memory elements) and a memory controller. The memory controller comprises a processor configured to process at least a part of an I/O command from a higher-level apparatus when the part of the I/O command satisfies a predetermined condition, and one or more hardware logic circuits configured to process the entire I/O command when the I/O command does not satisfy the predetermined condition.
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