公开(公告)号：US3727304A

公开(公告)日：1973-04-17

申请号：US3727304D

申请日：1970-09-28

Applicant: HONEYWELL INC

Inventor： GRANATO J ,  MOORE R

IPC: H01F10/06 ,  H01F7/06

CPC classification number: H01F10/06 ,  Y10T29/49069

Abstract: A plated wire thin film memory assembly and fabrication method is shown and described wherein the plated wire is contained in a ''''tunnel structure'''' sandwiched between layers of a multi-layer printed circuit assembly.

Abstract translation: 示出并描述了电镀线薄膜存储器组件和制造方法，其中电镀线被包含在夹在多层印刷电路组件的层之间的“隧道结构”中。