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公开(公告)号：US3755689A
公开(公告)日：1973-08-28
申请号：US3755689D
申请日：1971-12-30
IPC分类号： H03K19/096 , H03K19/08
CPC分类号： H03K19/096
摘要： Ratioless MOS logic circuits are disclosed which use two nonoverlapping clocks for two-phase control of signal propagation and a third precharge clock, of shorter duration, at double the repetition rate of the first two clocks for precharging storage node capacitance. In each circuit, an electrical network is provided having a transistor connected as a precharge diode for applying the precharge clock to the storage node capacitance through a clocked transfer gate transistor. A logic network is provided having a net of transistors connected, in parallel with the precharge diode transistor, as a relay logic network to selectively discharge the storage node capacitor, after the precharge clock. Where required, a novel dynamic buffer is provided having an output which is essentially insensitive to crossover capacitance effects.
摘要翻译： 公开了不可比较的MOS逻辑电路，其使用两个不重叠的时钟进行信号传播的两相控制，并且具有较短持续时间的第三预充电时钟，是用于预充电存储节点电容的前两个时钟的重复频率的两倍。 在每个电路中，提供电网，其具有作为预充电二极管连接的晶体管，用于通过时钟传输栅极晶体管将预充电时钟施加到存储节点电容。 提供了一个逻辑网络，其具有与预充电二极管晶体管并联连接的晶体管网，作为在预充电时钟之后选择性地对存储节点电容器进行放电的继电器逻辑网络。 在需要时，提供了一种新颖的动态缓冲器，其具有对交叉电容效应基本上不敏感的输出。
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公开(公告)号：US3813652A
公开(公告)日：1974-05-28
申请号：US32358673
申请日：1973-01-15
CPC分类号： G06F12/0676
摘要： A system is disclosed in which an input binary address is transformed into a set of module select signals and a set of address signals whereby an aggregate of memory modules, each of which may contain a different number of storage cells, are combined to form a memory assembly which has a fixed number of storage cells. The address transformation system uses signals taken from the individual modules which represent the number of memory cells contained therein.
摘要翻译： 公开了一种系统，其中输入二进制地址被变换成一组模块选择信号和一组地址信号，由此可以组合每个可以包含不同数量的存储单元的存储器模块的集合以形成存储器 具有固定数量的存储单元的组件。 地址转换系统使用从各个模块获取的信号，这些信号表示其中包含的存储器单元的数量。
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