Device for Compensating Temperature Drift of a VCO, and to a Method Thereof
    1.
    发明申请
    Device for Compensating Temperature Drift of a VCO, and to a Method Thereof 审中-公开
    用于补偿VCO的温度漂移的装置及其方法

    公开(公告)号:US20140354365A1

    公开(公告)日:2014-12-04

    申请号:US14461596

    申请日:2014-08-18

    CPC classification number: H03L1/023 H03L5/00 H03L7/099 H03L2207/06

    Abstract: A device for compensating temperature drift of a voltage controlled oscillator (VCO) is provided. The VCO has at least one varactor arranged for controlling an output frequency fOut of said VCO by applying a tuning voltage VTune and simultaneously applying a bias voltage VBias on a cathode and an anode of said at least one varactor, respectively. Said device comprises a monitoring circuit and a tuning circuit. Said monitoring circuit has an input arranged to receive said VTune and is arranged to monitor said VTune and further is arranged to activate said tuning circuit based on a value of said VTune, and said tuning circuit has an output connected to said anode and is arranged to output said VBias, wherein said tuning circuit further is arranged to tune said VCO by changing said VBias so as to compensate for a temperature drift of said VCO.

    Abstract translation: 提供了用于补偿压控振荡器(VCO)的温度漂移的装置。 VCO具有至少一个变容二极管,用于通过施加调谐电压VTune来控制所述VCO的输出频率fOut,同时分别在所述至少一个变容二极管的阴极和阳极上施加偏置电压VBias。 所述装置包括监视电路和调谐电路。 所述监视电路具有被布置为接收所述VTune的输入,并且被布置成监视所述VTune,并且还被布置为基于所述VTune的值激活所述调谐电路,并且所述调谐电路具有连接到所述阳极的输出,并被布置为 输出所述VBias,其中所述调谐电路还被布置为通过改变所述VBias来调谐所述VCO,以便补偿所述VCO的温度漂移。

    Interdigital Capacitor and Multiplying Digital-to-Analog Conversion Circuit

    公开(公告)号:US20220123762A1

    公开(公告)日:2022-04-21

    申请号:US17564437

    申请日:2021-12-29

    Abstract: An interdigital capacitor and a multiplying digital-to-analog conversion circuit are provided. The interdigital capacitor includes at least one first metal layer. The following components are disposed in each first metal layer: a first electrode; at least one first finger metal connected to the first electrode; a second electrode; and a plurality of second finger metals connected to the second electrode, and at least one third finger metal connected to the second electrode. The at least one first finger metal is alternately disposed with the plurality of second finger metals to form capacitors, and the at least one third finger metal is a dummy (dummy) finger metal.

    Signal Processing Arrangement for a Transmitter

    公开(公告)号:US20180191387A1

    公开(公告)日:2018-07-05

    申请号:US15909520

    申请日:2018-03-01

    Abstract: A signal processing arrangement for a transmitter includes an in-phase modulator configured to receive an in-phase signal (I) and configured to modulate the in-phase signal (I); a quadrature modulator configured to receive a quadrature signal (Q) and configured to modulate the quadrature signal (Q); an in-phase demodulator configured to demodulate the modulated in-phase signal (I) and to output a demodulated in-phase signal (I); a quadrature demodulator configured to demodulate the modulated quadrature signal (Q) and to output a demodulated quadrature signal (Q); an in-phase harmonic filter configured to perform a filtering on harmonics in the demodulated in-phase signal (I) and to output an in-phase digital signal (I); and a quadrature harmonic filter configured to perform a filtering on harmonics in the demodulated quadrature signal (Q) and to output a quadrature digital signal (Q).

    Signal processing arrangement for a transmitter

    公开(公告)号:US10516424B2

    公开(公告)日:2019-12-24

    申请号:US15909520

    申请日:2018-03-01

    Abstract: A signal processing arrangement for a transmitter includes an in-phase modulator configured to receive an in-phase signal (I) and configured to modulate the in-phase signal (I); a quadrature modulator configured to receive a quadrature signal (Q) and configured to modulate the quadrature signal (Q); an in-phase demodulator configured to demodulate the modulated in-phase signal (I) and to output a demodulated in-phase signal (I); a quadrature demodulator configured to demodulate the modulated quadrature signal (Q) and to output a demodulated quadrature signal (Q); an in-phase harmonic filter configured to perform a filtering on harmonics in the demodulated in-phase signal (I) and to output an in-phase digital signal (I); and a quadrature harmonic filter configured to perform a filtering on harmonics in the demodulated quadrature signal (Q) and to output a quadrature digital signal (Q).

    Receiver and wireless communications apparatus

    公开(公告)号:US10243600B2

    公开(公告)日:2019-03-26

    申请号:US15690860

    申请日:2017-08-30

    Abstract: Embodiments of the present invention provide a receiver and a wireless communications apparatus. The receiver includes: an attenuation circuit, configured to receive an input signal, and obtain a first signal according to the input signal; a low-noise amplification circuit, configured to receive the first signal, and obtain a second signal according to the first signal; an orthogonal down-frequency conversion circuit, configured to receive the second signal, and process the second signal to obtain an output signal; and a control circuit, configured to separately control the attenuation circuit and the low-noise amplification circuit according to power of an interference signal included in the output signal, so as to determine whether the attenuation circuit attenuates the input signal and whether the low-noise amplification circuit amplifies the first signal.

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