GRAPH COMPUTING APPARATUS, PROCESSING METHOD, AND RELATED DEVICE

    公开(公告)号:US20230195526A1

    公开(公告)日:2023-06-22

    申请号:US18171189

    申请日:2023-02-17

    CPC classification number: G06F9/5044 G06F9/30076

    Abstract: Embodiments of this application disclose apparatuses, processing methods, and related devices An example apparatus includes at least one processing engine (PE), and each of the at least one PE includes M status buffers, an arbitration logic circuit, and X operation circuits. Each of the M status buffers is configured to store status data of one iterative computing task. The arbitration logic circuit is configured to determine, based on the status data in the each of the M status buffers, L graph computing instructions to be executed in a current clock cycle, and allocate the L graph computing instructions to the X operation circuits. Each of the X operation-units circuits is configured to execute a graph computing instruction allocated by the arbitration logic circuit.

    GRAPH INSTRUCTION PROCESSING METHOD AND APPARATUS

    公开(公告)号:US20230120860A1

    公开(公告)日:2023-04-20

    申请号:US18067538

    申请日:2022-12-16

    Abstract: Disclosed are a graph instruction processing method and apparatus, which relates to the field of computer technologies One example method includes: detecting whether a first graph instruction has a conditional instruction element; and when the first graph instruction has the conditional instruction element, determining that the first graph instruction is a conditional execution instruction, and processing the first graph instruction when both data flow information and control flow information of the first graph instruction are in a ready state; or when the first graph instruction does not have a conditional instruction element, determining that the first graph instruction is a non-conditional execution instruction, and processing the first graph instruction when data flow information of the first graph instruction is in a ready state.

    PROCESSOR, PROCESSING METHOD, AND RELATED DEVICE

    公开(公告)号:US20230093393A1

    公开(公告)日:2023-03-23

    申请号:US18070781

    申请日:2022-11-29

    Abstract: This application discloses a processor, a processing method, and a related device. The processor includes a processor core. The processor core includes an instruction dispatching unit and a graph flow unit and at least one general-purpose operation unit that are connected to the instruction dispatching unit. The instruction dispatching unit is configured to: allocate a general-purpose calculation instruction in a decoded to-be-executed instruction to the at least one general-purpose calculation unit, and allocate a graph calculation control instruction in the decoded to-be-executed instruction to the graph calculation unit, where the general-purpose calculation instruction is used to instruct to execute a general-purpose calculation task, and the graph calculation control instruction is used to instruct to execute a graph calculation task. The at least one general-purpose operation unit is configured to execute the general-purpose calculation instruction. The graph flow unit is configured to execute the graph calculation control instruction.

    INSTRUCTION EXECUTION METHOD AND APPARATUS

    公开(公告)号:US20250165258A1

    公开(公告)日:2025-05-22

    申请号:US19029760

    申请日:2025-01-17

    Abstract: Embodiments of this application provide instruction execution methods and related apparatuses. An example method includes: determining that an execution status of a first block in a queue is a completed state, where the queue includes a plurality of blocks including the first block, the first block is a block with a smallest number in the queue, and the first block includes at least one instruction; changing a status of a processor based on an execution result of the at least one instruction in the first block; and deleting the first block from the queue.

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