公开(公告)号：US20240419443A1

公开(公告)日：2024-12-19

申请号：US18741186

申请日：2024-06-12

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Ruoyu ZHOU ,  Wenbo SUN ,  Jianjiang ZENG ,  Guozhu LI ,  Xiping ZHOU ,  Heng LIAO

IPC: G06F9/26

Abstract: Embodiments of this application provide example computing chips and instruction processing method related to the field of integrated circuit technologies. One example computing chip uses a superscalar processor architecture, and includes an instruction processing unit and a plurality of registers that are separately coupled to the instruction processing unit. The plurality of registers include a general purpose register and a plurality of private registers that are separately coupled to the general purpose register. The general purpose register is configured to store an execution result of a microinstruction that is in a plurality of microinstructions of a computing task and that is executed before a jump instruction and whose execution result is referenced by a microinstruction that is executed after the jump instruction. Each private register in the plurality of private registers is configured to store an execution result of any microinstruction in the plurality of microinstructions.

公开(公告)号：US20230120860A1

公开(公告)日：2023-04-20

申请号：US18067538

申请日：2022-12-16

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Ruoyu ZHOU ,  Fan ZHU ,  Wenbo SUN ,  Xiping ZHOU

IPC: G06F9/30

Abstract: Disclosed are a graph instruction processing method and apparatus, which relates to the field of computer technologies One example method includes: detecting whether a first graph instruction has a conditional instruction element; and when the first graph instruction has the conditional instruction element, determining that the first graph instruction is a conditional execution instruction, and processing the first graph instruction when both data flow information and control flow information of the first graph instruction are in a ready state; or when the first graph instruction does not have a conditional instruction element, determining that the first graph instruction is a non-conditional execution instruction, and processing the first graph instruction when data flow information of the first graph instruction is in a ready state.

公开(公告)号：US20230093393A1

公开(公告)日：2023-03-23

申请号：US18070781

申请日：2022-11-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Xiping ZHOU ,  Ruoyu ZHOU ,  Fan ZHU ,  Wenbo SUN

IPC: G06F9/30

Abstract: This application discloses a processor, a processing method, and a related device. The processor includes a processor core. The processor core includes an instruction dispatching unit and a graph flow unit and at least one general-purpose operation unit that are connected to the instruction dispatching unit. The instruction dispatching unit is configured to: allocate a general-purpose calculation instruction in a decoded to-be-executed instruction to the at least one general-purpose calculation unit, and allocate a graph calculation control instruction in the decoded to-be-executed instruction to the graph calculation unit, where the general-purpose calculation instruction is used to instruct to execute a general-purpose calculation task, and the graph calculation control instruction is used to instruct to execute a graph calculation task. The at least one general-purpose operation unit is configured to execute the general-purpose calculation instruction. The graph flow unit is configured to execute the graph calculation control instruction.

公开(公告)号：US20230195526A1

公开(公告)日：2023-06-22

申请号：US18171189

申请日：2023-02-17

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Ruoyu ZHOU ,  Fan ZHU ,  Wenbo SUN ,  Xiping ZHOU

IPC: G06F9/50 ,  G06F9/30

CPC classification number: G06F9/5044 ,  G06F9/30076

Abstract: Embodiments of this application disclose apparatuses, processing methods, and related devices An example apparatus includes at least one processing engine (PE), and each of the at least one PE includes M status buffers, an arbitration logic circuit, and X operation circuits. Each of the M status buffers is configured to store status data of one iterative computing task. The arbitration logic circuit is configured to determine, based on the status data in the each of the M status buffers, L graph computing instructions to be executed in a current clock cycle, and allocate the L graph computing instructions to the X operation circuits. Each of the X operation-units circuits is configured to execute a graph computing instruction allocated by the arbitration logic circuit.