公开(公告)号：US20230361082A1

公开(公告)日：2023-11-09

申请号：US18341880

申请日：2023-06-27

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Shan GAO ,  Jifeng ZHU ,  Dian LEI

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/32 ,  H01L24/16 ,  H01L24/73 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2224/32146 ,  H01L2224/16146 ,  H01L2224/73253 ,  H01L2924/37001

Abstract: A chip stacking structure includes a plurality of chips that are sequentially stacked and a first redistribution layer arranged on an active side of each chip. The plurality of chips include a first chip and a second chip that are located on an outermost side. Passive sides of the first chip and the second chip both face an outer side, and the chip stacking structure further includes a second redistribution layer arranged on the passive side of the first chip or the second chip. The second redistribution layer is electrically connected to at least one first redistribution layer through a first via hole.