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公开(公告)号:US20220077018A1
公开(公告)日:2022-03-10
申请号:US17526966
申请日:2021-11-15
Applicant: HUAWEI TECHNOLOGIES CO.,LTD.
Inventor: Mao Guo , Yiwei Ren , Xiaodong Zhang
Abstract: A chip packaging apparatus and a preparation method thereof are provided, to modulate warpage of a chip, thereby resolving a problem of mismatch between a warpage degree of the chip and a warpage degree of a substrate. The chip packaging apparatus includes a chip, a substrate, and a warpage modulation structure, where a surface that is of the chip and that faces the substrate is electrically connected to the substrate, the warpage modulation structure is disposed on a surface that is of the chip and that is opposite to the substrate, and a coefficient of thermal expansion of the warpage modulation structure is greater than a coefficient of thermal expansion of the chip.
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公开(公告)号:US20220189901A1
公开(公告)日:2022-06-16
申请号:US17687220
申请日:2022-03-04
Applicant: Huawei Technologies Co., Ltd.
Inventor: Shiqun Gu , Rui Niu , Xiaodong Zhang , Yiwei Ren , Tonglong Zhang
IPC: H01L23/00 , H01L23/538 , H01L25/10 , H01L25/065 , H01L25/00
Abstract: A packaged IC includes a fanout layer, a processor having a first surface residing substantially adjacent a first surface of the fanout layer, a Redistribution Layer (RDL) having a first surface coupled to a second surface of the processor, and a memory coupled to a second surface of the RDL, wherein a first portion of the memory is disposed outside of a footprint of the processor and a second portion of the memory is disposed within the footprint of the processor. The packaged IC further includes first conductive posts disposed beneath the first portion of the memory proximate a first side of the processor for providing communication links between the processor and memory, and second conductive posts coupled between the fanout layer and conductive features of the RDL coupled to power inputs of the second portion of the memory, the second conductive posts proximate a second side of the processor.
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