POWER SUPPLY CIRCUIT AND FREQUENCY ADJUSTMENT METHOD

    公开(公告)号:US20240427406A1

    公开(公告)日:2024-12-26

    申请号:US18824694

    申请日:2024-09-04

    Abstract: A power supply circuit and a frequency adjustment method are provided, to improve running stability of a processing module (200). The power supply circuit obtains an operating voltage of the processing module (200), and generates, based on the operating voltage, a clock signal that indicates an operating frequency of the processing module (200), so that the processing module (200) runs at an operating frequency corresponding to a current operating voltage. Even if the operating voltage fluctuates, running of the processing module (200) is not affected. This improves running stability of the processing module (200) without increasing power consumption.

    Mobile edge computing method and apparatus

    公开(公告)号:US11803409B2

    公开(公告)日:2023-10-31

    申请号:US17099436

    申请日:2020-11-16

    Abstract: A mobile edge computing method and apparatus are provided. The method which is implemented by a mobile edge computing (MEC) management network element includes: receiving an MEC virtualization resource request sent by a control plane of a target radio access network (RAN), wherein the control plane belongs to the target RAN to which user equipment (UE) is handed over, and the MEC virtualization resource request includes an MEC computing resource requirement of the UE; creating, based on the MEC virtualization resource request, a new virtual machine (VM) on an MEC server for the UE, wherein the new VM is used on the target RAN side after the handover; and sending first information of the new VM to the control plane, wherein the first information includes an ID of the new VM. According to the application, the efficiency of usage of resources during a handover of UE is significantly improved.

    Method and apparatus for managing storage device in storage system

    公开(公告)号:US11314454B2

    公开(公告)日:2022-04-26

    申请号:US16912377

    申请日:2020-06-25

    Abstract: In a method for accessing a storage system, a client in the storage system identifies a logical address of a storage device, and queries a management server regarding a mapping between the storage device and a start address of a submission queue (SQ) in the memory of the storage node. The client then sends an access request including the logical address of the storage device directed to the start address of the SQ to a network interface card NIC of the storage node. The NIC receives and sends the access request to the start address of the SQ in the memory. The storage device obtains the access request from the start address of the SQ and executes the access request.

    Data protection circuit of chip, chip, and electronic device

    公开(公告)号:US11216593B2

    公开(公告)日:2022-01-04

    申请号:US16411230

    申请日:2019-05-14

    Abstract: A data protection circuit of a chip, a chip, and an electronic device, where the data protection circuit performs bit width expansion and scrambling processing on a first alarm signal using an operation circuit to obtain a second alarm signal, and outputs the second alarm signal to a processing circuit. The processing circuit performs descrambling processing after receiving the second alarm signal to obtain a descrambling result. When the second alarm signal is attacked, the descrambling fails, and the descrambling result is an active level. The processing circuit outputs the descrambling result to a reset request circuit, and the reset request circuit generates a reset request signal according to the descrambling result.

    METHOD AND APPARATUS FOR MANAGING STORAGE DEVICE IN STORAGE SYSTEM

    公开(公告)号:US20200326891A1

    公开(公告)日:2020-10-15

    申请号:US16912377

    申请日:2020-06-25

    Abstract: In a method for accessing a storage system, a client in the storage system identifies a logical address of a storage device, and queries a management server regarding a mapping between the storage device and a start address of a submission queue (SQ) in the memory of the storage node. The client then sends an access request including the logical address of the storage device directed to the start address of the SQ to a network interface card NIC of the storage node. The NIC receives and sends the access request to the start address of the SQ in the memory. The storage device obtains the access request from the start address of the SQ and executes the access request.

    Method, device, and system for implementing hardware acceleration processing

    公开(公告)号:US10365830B2

    公开(公告)日:2019-07-30

    申请号:US15786207

    申请日:2017-10-17

    Abstract: A method, device, and system for implementing hardware acceleration processing, where the method includes memory mapping input/output (MMIO) processing being performed on a data buffer address of a hardware acceleration processor in order to obtain an address in addressing space of a central processing unit (CPU). In addition, a network adapter has a remote direct memory access (RDMA) or a direct memory access (DMA) function. Alternatively, a network adapter of a hardware acceleration device can directly send received data on which the hardware acceleration processing is to be performed to a hardware acceleration processor. In this way, resource consumption is reduced when the CPU of a computer device receives and forwards the data on which the hardware acceleration processing is to be performed, and in addition, storage space of a memory of the computer device is saved.

    Method, device and system for performing bidirectional forwarding detection on aggregated link

    公开(公告)号:US10218592B2

    公开(公告)日:2019-02-26

    申请号:US15639761

    申请日:2017-06-30

    Abstract: A method for performing bidirectional forwarding detection (BFD) on an aggregated link between a first network device and a second network device, where the first network device sends, to the second network device, information used to establish at least two BFD sessions. The first network device receives information that is used to establish at least two BFD sessions and sent by the second network device. The first network device respectively establishes BFD sessions between at least two pairs of ports according to the stored information and the information sent by the second network device. The first network device determines whether at least one BFD session in the established BFD sessions is up. If at least one BFD session in the established BFD sessions is up, the first network device determines that the aggregated link between the first network device and the second network device is available.

    Reflector antenna and reflector antenna feed

    公开(公告)号:US10193221B2

    公开(公告)日:2019-01-29

    申请号:US15674112

    申请日:2017-08-10

    Inventor: Yu Liu

    Abstract: Embodiments of the present invention provide a reflector antenna and a reflector antenna feed. The reflector antenna feed includes a transmit antenna array and a receive antenna array, where the transmit antenna array includes at least two transmit antenna units. The receive antenna array includes at least two receive antenna units. Also, a phase center of the transmit antenna array coincides with that of the receive antenna array, where at least one coupling unit is disposed between at least one group of a transmit antenna unit and a receive antenna unit that are adjacent to each other.

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