Residue free vertical pattern transfer with top surface imaging resists
    1.
    发明授权
    Residue free vertical pattern transfer with top surface imaging resists 失效
    残留自由垂直图案转印与顶部表面成像抗蚀剂

    公开(公告)号:US5312717A

    公开(公告)日:1994-05-17

    申请号:US949963

    申请日:1992-09-24

    IPC分类号: G03F7/26 G03F7/36 G03C5/00

    CPC分类号: G03F7/36 G03F7/265

    摘要: A method for transferring a pattern through a photoresist layer in the fabrication of submicron semiconductor devices structures is disclosed. A photoresist is provided on a substrate and the same is imagewise exposed with a desired pattern to form exposed and unexposed patterned areas in the top surface of the photoresist. The photoresist is then baked to form cross-linked regions in the exposed pattern areas of the photoresist. Silylation is then performed to incorporate silicon into the unexposed patterned areas of the photoresist, wherein some incorporation of silicon occurs in the exposed patterned crosslinked areas of the photoresist. The patterned photoresist is subsequently etched using a high density, low pressure, anisotropic O.sub.2 plasma alone to produce residue-free images with vertical wall profiles in the photoresist. This method is particularly advantageous with RFI reactive ion etch systems.

    摘要翻译: 公开了在制造亚微米半导体器件结构中通过光致抗蚀剂层转印图案的方法。 在基板上提供光致抗蚀剂,并将其以所需图案成像曝光,以在光致抗蚀剂的顶表面中形成曝光和未曝光的图案区域。 然后将光致抗蚀剂烘烤以在光致抗蚀剂的暴露图案区域中形成交联区域。 然后进行硅烷化以将硅结合到光致抗蚀剂的未曝光图案区域中,其中硅的一些掺入发生在光致抗蚀剂的暴露的图案化交联区域中。 随后使用高密度,低压,各向异性O 2等离子体蚀刻图案化的光致抗蚀剂,以在光致抗蚀剂中产生具有垂直壁分布的无残留图像。 该方法对于RFI反应离子蚀刻系统是特别有利的。

    Planarized silicon fin device
    2.
    发明授权
    Planarized silicon fin device 有权
    平面化硅片装置

    公开(公告)号:US06252284B1

    公开(公告)日:2001-06-26

    申请号:US09458531

    申请日:1999-12-09

    IPC分类号: H01L2976

    摘要: An improved fin device used as the body of a field effect transistor (“FET”) and an improved process of making the fin device. The fin device allows for the fabrication of very small dimensioned metal-oxide semiconductor (“MOS”) FETs in the size range of micrometers to nanometers, while avoiding the typical short channel effects often associated with MOSFETs of these dimensions. Accordingly, higher density MOSFETs may be fabricated such that more devices may be placed on a single semiconductor wafer. The process of making the fin device results in an improved fully planarized device.

    摘要翻译: 用作场效应晶体管(“FET”)的主体的改进的鳍装置以及制造鳍片装置的改进方法。 翅片器件允许制造尺寸范围为微米至纳米的非常小尺寸的金属氧化物半导体(“MOS”)FET,同时避免通常与这些尺寸的MOSFET相关的典型的短沟道效应。 因此,可以制造更高密度的MOSFET,使得可以在单个半导体晶片上放置更多的器件。 制造翅片装置的过程导致改进的完全平坦化的装置。

    Process for making planarized silicon fin device

    公开(公告)号:US06432829B1

    公开(公告)日:2002-08-13

    申请号:US09801473

    申请日:2001-03-08

    IPC分类号: H01L21302

    摘要: An improved fin device used as the body of a field effect transistor (“FET”) and an improved process of making the fin device. The fin device allows for the fabrication of very small dimensioned metal-oxide semiconductor (“MOS”) FETs in the size range of micrometers to nanometers, while avoiding the typical short channel effects often associated with MOSFETs of these dimensions. Accordingly, higher density MOSFETs may be fabricated such that more devices may be placed on a single semiconductor wafer. The process of making the fin device results in an improved fully planarized device.