公开(公告)号：US06438658B1

公开(公告)日：2002-08-20

申请号：US09609072

申请日：2000-06-30

申请人： Harikrishna B. Baliga ,  Subramaniam Maiyuran ,  Salvador Palanca

发明人： Harikrishna B. Baliga ,  Subramaniam Maiyuran ,  Salvador Palanca

IPC分类号： G06F1200

CPC分类号： G06F12/0891

摘要： A method and apparatus for single cycle, cache line invalidation within a cache memory is described. The method includes enabling memory cells within a cache state array of the cache memory. An invalid state is then written to each memory cell within the cache state array of the cache memory. The enabling of the memory cells within the cache state array of the cache memory occurs during a first phase of a clock cycle. While the writing of the invalid state to each memory cell within the cache state array of the cache memory occurs during a second phase of the clock cycle. Consequently, cache line invalidation of each cache line within the cache memory occurs within a single clock cycle formed by the first phase of the clock cycle and the second phase of the clock cycle. In partial invalidation of the cache memory is possible by way-subdividing the cache state array or set-subdividing the cache state array. One shot or single cycle cache line invalidation reduces the total time required for invalidation of all cache lines within the cache memory to just a clock cycle. The implementation is simple with minimal changes to the cache array limited only to those cells that store the state information of the cache lines. Since many system operations necessitate invalidation of the entire cache, one-shot invalidation clearly improves the system performance with no significant impact on the die size.

摘要翻译： 描述了用于单周期，高速缓冲存储器内的高速缓存行无效的方法和装置。 该方法包括启用高速缓冲存储器的高速缓存状态阵列内的存储单元。 然后将无效状态写入高速缓冲存储器的高速缓存状态阵列内的每个存储单元。 高速缓冲存储器的高速缓存状态阵列内的存储单元的使能在时钟周期的第一阶段期间发生。 当在时钟周期的第二阶段期间，将无效状态写入到高速缓冲存储器的高速缓存状态阵列内的每个存储器单元。 因此，高速缓冲存储器内的每个高速缓存行的高速缓存行无效发生在由时钟周期的第一阶段和时钟周期的第二阶段形成的单个时钟周期内。 通过对高速缓存状态数组进行细分，或者对高速缓存状态数组进行分组，可以使高速缓冲存储器部分失效。 单次或单周期高速缓存行无效将将缓存中所有高速缓存行无效的总时间减少到仅仅一个时钟周期。 该实现是简单的，对缓存阵列的最小变化仅限于存储高速缓存行状态信息的那些单元。 由于许多系统操作需要使整个高速缓存无效，一次性无效显然提高了系统性能，对芯片尺寸没有显着的影响。

公开(公告)号：US06965970B2

公开(公告)日：2005-11-15

申请号：US09967031

申请日：2001-09-27

申请人： Lokpraveen B. Mosur ,  Harikrishna B. Baliga

发明人： Lokpraveen B. Mosur ,  Harikrishna B. Baliga

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0804

摘要： An apparatus and a method for rapidly flushing a cache memory device, including a list structure to track changes in a cache, which may be implemented on the processor die separate from the cache memory. The list structure allows for access to a relatively small store of data to determine whether or not a cache entry needs to be written to the main memory. Choosing the format of the list structure, allows one to make tradeoffs between area needed on a chip and the amount of efficiency in the cache flushing process.

摘要翻译： 一种用于快速冲洗高速缓冲存储器设备的装置和方法，该缓存存储器设备包括列表结构以跟踪高速缓存中的变化，其可以在处理器管芯上实现，与高速缓冲存储器分离。 列表结构允许访问相对较小的数据存储以确定高速缓存条目是否需要写入主存储器。 选择列表结构的格式，允许人们在芯片所需的区域与缓冲区冲洗过程中的效率之间进行权衡。

公开(公告)号：US07266647B2

公开(公告)日：2007-09-04

申请号：US11280585

申请日：2005-11-15

申请人： Lokpraveen B. Mosur ,  Harikrishna B. Baliga

发明人： Lokpraveen B. Mosur ,  Harikrishna B. Baliga

IPC分类号： G06F12/00

CPC分类号： G06F12/0804

摘要： An apparatus and a method for rapidly flushing a cache memory device, including a list structure to track changes in a cache, which may be implemented on the processor die separate from the cache memory. The list structure allows for access to a relatively small store of data to determine whether or not a cache entry needs to be written to the main memory. Choosing the format of the list structure, allows one to make tradeoffs between area needed on a chip and the amount of efficiency in the cache flushing process.

摘要翻译： 一种用于快速冲洗高速缓冲存储器设备的装置和方法，该缓存存储器设备包括列表结构以跟踪高速缓存中的变化，其可以在处理器管芯上实现，与高速缓冲存储器分离。 列表结构允许访问相对较小的数据存储以确定高速缓存条目是否需要写入主存储器。 选择列表结构的格式，允许人们在芯片所需的区域与缓冲区冲洗过程中的效率之间进行权衡。

公开(公告)号：US08775990B1

公开(公告)日：2014-07-08

申请号：US13929102

申请日：2013-06-27

申请人： Peter J. Smith ,  Bharat S. Pillilli ,  Harikrishna B. Baliga ,  Michael S. Yu ,  Shlomi Alkalay

发明人： Peter J. Smith ,  Bharat S. Pillilli ,  Harikrishna B. Baliga ,  Michael S. Yu ,  Shlomi Alkalay

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G01R31/3177

摘要： Techniques for controlling alignment of conditions between modular functional blocks in an integrated circuit having a hierarchical network of modular functional blocks. The output of each functional block can be logically determined by its external inputs combined with internal state feedback and internal state and is derived from a pattern of prior external inputs. Alignment of output conditions from independent and interdependent functional blocks within the hierarchical network of functional blocks is induced to provide unique conditions by modifying internal state and timing alignments with internal data and internal controls within one or more of the modular functional blocks. Functional outputs from one or more of the modular functional blocks can be monitored based on the modified internal state and timing alignments. Pattern results can be generated based on the monitoring. Test results based on the pattern results can be stored.

摘要翻译： 用于控制具有模块化功能块的分层网络的集成电路中的模块化功能块之间的条件对准的技术。 每个功能块的输出可以通过其外部输入结合内部状态反馈和内部状态在逻辑上确定，并且从先前的外部输入的模式导出。 通过在一个或多个模块化功能块内修改与内部数据和内部控制的内部状态和定时对准，来诱导功能块分级网络内独立和相互依赖的功能块的输出条件的对准，从而提供独特的条件。 可以基于修改的内部状态和定时对准来监视来自一个或多个模块化功能块的功能输出。 模式结果可以基于监控生成。 可以存储基于模式结果的测试结果。